MathWorks couples Xilinx FPGAs to Simulink - Embedded.com

MathWorks couples Xilinx FPGAs to Simulink

In design of algorithm-intensive ICs, simulation at high levels ofabstraction is mandatory. Simulation begins at the mathematical level,testing algorithms against data sets. It ends with net list-levelfunctional verification runs. Tools for both of these undertakings arewell-understood. The challenge comes in between, when parts of thedesign remain in algorithmic form, parts are under development asbehavioral or transaction-level code such as SystemC, and reused IPblocks already exist in RTL. Even in a multi-mode simulationenvironment, traversing a test case can be crushingly slow, draggeddown by the level of detail in the RTL simulation.

MathWorks has clearly encountered this issue when customers use theSimulink co-simulation block. Efficiently handling transactions betweensimulators doesn't make the simulations run faster. In response, thecompany today introduced EDA Simulator Link 3.3, with the ability tocouple an FPGA emulation – via any of several Xilinx development boars- into the Simulink co-simulation environment.

Ken Karnofsky, director of marketing at MathWorks, explained theapproach. A user would select a supported Spartan or Virtex board andinstall it in the normal way. Then the team would select the RTL theyintend to put in the FPGA – either existing design RTL, test-benchcode, or algorithmic RTL created by the MathWorks HDL code generator.This code goes through the normal Xilinx tool chain, along withinterface code to connect to Simulink, and from there in to the FPGA.Simulink then executes transactions with the FPGA as if the chip werean external simulator.

The FPGA operates at full hardware speed, producing transactions ordersof magnitude faster than an RTL simulation. There are limitations incontrolability and observability, as there would be for any FPGAemulation. It appears that the designers must define ahead of time thetransactions between Simulink and the FPGA. And Karnofsky said theapproach requires familiarity with FPGA use, since after all the teamis taking an RTL design through the Xilinx design flow.

EDA Simulator Link 3.3, with FPGA-in-the-loop capability andconnections for Cadence Incisive Enterprise Simulator and Mentor'sModelSim and Questa, is available now, with list prices starting at$2,000 US.

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