Memory compilers, logic libraries fit TSMC's 40-nm process - Embedded.com

Memory compilers, logic libraries fit TSMC’s 40-nm process

Virage Logic's memory compilers and logic libraries can now be used with TSMC's 40-nm process. The company's SiWare product portfolio provides semiconductor companies with 40-nm physical IP that potentially enables SoCs to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields. The SiWare product line was previously available for the 65-nm process.

This introduction addresses the increasingly complex design requirements placed on physical IP at advanced process nodes. The compilers and logic libraries give designers a complete “dashboard” of options for maximum flexibility to effectively manage design tradeoffs to meet their specific requirements.

Primary end markets for SiWare IP on TSMC's 40G process include computer, graphics, networking and storage applications, while primary end markets for SiWare IP on TSMC's 40LP process include wireless, battery-operated and Virage Logic SiWare 40-nm consumer applications. Users can achieve static power savings of up to 35%, 70%, and 90%, depending on their selection of the built-in light sleep, deep sleep, and shut-down modes available in both the 40G and 40LP memories.

The SiWare Memory product line of silicon-aware compilers provides power-optimized memories for advanced processes. These compilers minimize both static and dynamic power consumption and provide optimal yields. They also result in a minimal area usage. Compile-time options for process threshold variants, power saving modes, read and write margin extensions, ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.

SiWare Memory compilers and SiWare Logic libraries are available now for early adopters of TSMC's 40G and 40LP processes. Early partners already have internally qualified SiWare IP in silicon. Virage Logic's qualification process, based on advanced test chip methodologies, is in progress and will be finalized as early as July 2008. Project pricing starts at $100,000. The SiWare product portfolio supports all major electronic design automation (EDA) tool flows targeted for the 40nm process including Cadence Design Systems, Magma Design Automation and Synopsys. More information can be found at www.viragelogic.com.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.