The new Mentor EZ-VIP PCI Express Verification IP from Mentor Graphics Corp. reduces testbench assembly time for ASIC (application-specific integrated circuit) and FPGA (field-programmable gate array) design verification by a factor of up to 10X.
Verification IP is intended to help engineers reduce the time spent building testbenches by providing re-usable building blocks for common protocols and architectures. However, even standard protocols and common architectures can be configured and implemented differently from design to design. As a result, traditional VIP components can take days, or even weeks, to prepare for a simulation or emulation testbench.
Unlike traditional verification IP, Mentor’s new PCIe EZ-VIP is “design-aware,” eliminating several time-consuming steps in the testbench assembly process. This fast-forwards verification engineers past tedious configuration and implementation set-up tasks, directly to high-value scenario generation, reducing a process that used to take days or weeks to just hours.
Mentor’s PCIe EZ-VIP includes pre-packaged, easy-to-use verification environments for the serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0 and mPCIe, which can be used to verify PHY, Root Complex and Endpoint designs. Test plans, compliance tests, test sequences, and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.