Mentor extends embedded design into ESL -

Mentor extends embedded design into ESL

San Diego, Ca. – At the Design Automation Conference here Mentor Graphics took the wraps off a new unified embedded software debugging platform, from pre-silicon to final product.

It combines Mentor’s Sourcery CodeBench embedded software development tools with its electronic system level (ESL), verification, and hardware emulation products: Vista Virtual Prototyping, Veloce hardware emulator, prototype target boards, and end products.

According to Wally Rhines, CEO of Mentor Graphics, the new common platform is designed to allow embedded software developers to access technology data from hardware design tools without leaving their native embedded software environment.

The Sourcery CodeBench product was derived from the December 2010 Mentor-acquired Sourcery G++ technology – the de facto standard for embedded Linux and bare metal software development, with over 20,000 registered users.

He said the common platform provides the flexibility to run unified embedded software debug and analysis at any stage of development, making it an ideal solution for earlier visibility of system performance and embedded software validation.

This enables upfront and continuous retooling of today’s complex SoCs and multicore designs, resulting in greater accuracy, optimized performance, and faster product delivery.

The Sourcery CodeBench IDE is based on the GNU toolchain and its SystemAnalyzer provides a system-level visual analysis capability that allows developers to see what is running on each software core to identify bottlenecks, gain insight on resource utilization, and to build more reliable multicore systems.

The host software target generated by the tool includes a unique unified trace and debug data repository of code that can be tested across the evolving range of hardware representations.

This technology provides consistency and flexibility throughout the entire system-level development flow by enabling hardware and software designers to select their preferred methodology for embedded software debug and design optimization, from virtual prototypes to boards.

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