Mentor Graphics and EnSilica partner on FPGA IP platform -

Mentor Graphics and EnSilica partner on FPGA IP platform

EnSilica (Wokingham, UK) has become a partner for Mentor Graphics’ Precise-IP vendor-independent FPGA IP platform and its range of eSi-RISC embedded processor cores and eSi-Comms library of communications IP has been fully validated for use in Mentor Graphics’ Precision Synthesis FPGA design flow.
EnSilica's eSi-RISC is a family of highly configurable and low-power soft processor cores for embedded systems that scales across a range of applications.  It is scalable from 16 bits to 32 bits, and encompassing optional DSP extensions, floating point and custom instructions. It was first released in November 2009.

The memory architecture can be configured for Harvard or Von Neumann, or to include data and program caches.  Using a mix of 16-bit and 32-bit instructions, it gives exceptional code density, reducing the program code size by up to 40 percent compared to leading FPGA vendor processors such as NIOSII and MicroBlaze while the minimum configuration can be implemented in as little as 8K gates, providing class leading overall silicon area and very low power.

System clock speeds of over 200MHz can be achieved in Altera Stratix IV and Xilinx Virtex-6 FPGAs and all processors use the industry standard AMBA APB and AXI buses. EnSilica also has a library of APB-based peripherals, including UART, SPI, I2C, Timers and a 10/100 Ethernet MAC.
EnSilica’s eSi-Comms library of highly parameterized communications IP is suitable for many of the current air interface standards including WLAN, WiMAX, DVB and DAB.
Precise-IP is Mentor Graphics’ vendor-independent FPGA IP platform.  It is part of the Precision Synthesis product family that includes RTL, physical and rad-tolerant synthesis tools. Precision Synthesis is the center-piece of the industry's most comprehensive vendor-independent solution for FPGA design. The tool uses the same design source and constraints to target all major device vendors, enabling designers to synthesize eSi-RISC processors and eSi-Comms IP for optimal performance on any FPGA technology.

In March 2010 EnSilica updated the eSi-RISC development suite.


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