Mentor Graphics Corporation has released a new version of the Mentor Embedded Nucleus real time operating system (RTOS) targeting high-performance, next-generation applications for connected embedded devices. The Nucleus RTOS process model is expanded to include ARM Cortex M-based cores. Software developers can use a single embedded operating system to increase system reliability through memory partitioning for the entire spectrum of ARM cores, facilitating code reuse across an entire product family comprising low-end to high-end devices. New in this release is a multicore framework to manage inter-process communication (IPC) and processor life cycle for complex heterogeneous system-on-chip (SoC) and enhanced Nucleus RTOS graphics capabilities with Imagination and Vivante GPU support.
Nucleus RTOS is scalable to conform to resource limitations typical of microcontroller (MCU)-based devices while still providing space partitioning to improve system reliability. By using the memory protection unit (MPU) on ARM Cortex M- based cores, the Nucleus RTOS process model creates memory partitioning without the need to implement virtual memory, maintaining a lightweight operating environment that can be executed in devices with limited memory by “executing in place” out of flash devices. The Nucleus RTOS process model improves system reliability for devices with aggressive dependability requirements, and for devices with safety requirements such as those designed for industrial and medical devices.
Nucleus RTOS includes the Mentor Embedded Multicore Framework (MEMF) for asymmetric multi-processing (AMP) enablement. Based on a clean-room implementation of the functionality in “virtIO”, “remoteproc”, and “rpmsg”, MEMF enables developers to integrate Nucleus RTOS, Linux, and bare metal-based applications and manage the challenges associated with IPC, resource sharing, and processor control within a heterogeneous multi-OS environment. Developers can control the boot-up and shut-down of individual cores on a SoC, allowing applications to maximize compute performance or minimize power consumption based on the use case.