Microsemi announced its collaboration with MathWorks to launch hardware support for FPGA-in-the-loop (FIL) verification workflow with Microsemi FPGA development boards. The new integrated FIL workflow with HDL Coder and HDL Verifier from MathWorks enables customers to automatically generate test benches for hardware description language (HDL) verification, including VHSIC Hardware Description Language (VHDL) and Verilog, providing rapid prototyping and verification of designs.
The collaboration with MathWorks enables customers to integrate MATLAB, a programming environment for algorithm development, data analysis, visualization and numeric computation, and Simulink, a graphical environment for simulation and Model-Based Design, with Microsemi’s SmartFusion 2 SoC FPGA and PolarFire FPGA development boards, which allows the stimulation of designs through FIL verification workflow using Microsemi’s development boards. FIL verification workflow enables customers to analyze the results back in MATLAB and Simulink.
Microsemi’s Accelerate Ecosystem facilitates collaboration between Microsemi and leading firms in the semiconductor integrated circuit, IP, systems, software, tools and design spaces to integrate, test and deliver pre-validated designs and system-level solutions for end customers in Microsemi’s key vertical markets—aerospace and defense, data center, communications and industrial.