PCB and embedded systems designers are scratching their heads these days, facing some uncertainty as they start mapping out the move from DDR3 SDRAM to DDR4. Routing DDR2 signals on a PCB was tough enough. But with DDR3 it proved to be even more difficult and challenging. The big question now is: will DDR4 be just as much of a challenge? More? Or less?
Double data rate synchronous dynamic random-access memory (DDR SDRAM) is the most commonly used class of memory integrated circuits used in today’s microprocessor-based systems. DDR SDRAM, also called DDR1 SDRAM, over the years was superseded by DDR2 SDRAM and DDR3 SDRAM, neither of which is backward compatible with DDR1 SDRAM. As a result, DDR2 or DDR3 memory modules will not work in DDR1-equipped printed circuit boards. The trend continues with DDR4 and it is up to PCB designers to make it work.
To make the transition from earlier DDRAM versions to DDR4, it is important to review the main differences between DDR2 and DDR3 and find out what can be learned that will be useful transitioning printed circuit board designs to DDR4.
Schemes versus architectures
Industry discussions relating to DDR often talk about fly-by and point-to-point “architectures.” For the purposes of clarity in this article the main focus is on the I/O architecture of the DDR devices and discussions of specific uses within that context will use the word ‘scheme’. In this article, ‘fly-by schemes’ applies to termination only. When the term ‘architecture’ is used, it refers to I/O architecture.
Fly-by, as used in DDR3 devices, is a scheme by which to connect the command and address signals in series with each of the memory modules, along with appropriate termination at the end. The signals travelling in this topology reach different memory modules at different time intervals and encounter the input capacitive load of the memory modules in a delayed fashion.
DDR2 – DDR3 similarities and differences
The main differences between DDR2 and DDR3 are: Noise margins are far less for DDR3 than for DDR2. Clock routing in particular is critical here. DDR3 uses differential clocks and they need to be length-matched as well as impedance-controlled. The length of the clock signal has to be length-matched to the lengths of signals in the address and command group.
When length matching, the most important thing to keep in mind is the difference between the signal lengths within a given DDR byte lane and that of its strobe. So for DQS (Data Queue Strobe) and DM (Data Mask) lines the maximum deviation has to be ±/10 picoseconds. Translated into length, that’s around ±/50 mils on a PCB’s FR4 glass-reinforced epoxy laminate material.
This doesn’t allow much leeway when length-matching the signals. For many PCB and embedded designers, this is quite a challenge, especially when working with very tight spaces. The more cramped the space, the more difficult it is to match those lengths. Figure 1 shows length-matching for a DDR3 PCB layout.
With so many different types of signals intertwined in DDR3, the designer has to be both proactive and interactive when routing these signals. Once a signal is routed and goes out of spec with another trace, the designer has to go to the other trace to tune it. In the end, he or she must have a well designed system so that all trace lines and spacing are properly managed and lengths are matched with the groups. It is therefore very important to route the longest lane first.
Ideally, the goal is to have equal signal lengths in the address and command groups. Also, mismatched transmission lines to vias must be avoided. In most cases vias should not be used. The one exception is in PCBs that incorporate ball grid array (BGA) circuit packages.
Routing address and command signals in a daisy chain topology represents a major change between DDR2 and DDR3 routing. Maximum length between the first SDRAM and the last one in the chain must not be more than five inches.
Impact of DDR2/DDR3 differences on PCB designs
The main differences between DDR2 and DDR3 is that DDR3 has a faster frequency, improved power delivery, greater package reliability, improved pin placement, and fly-by termination. DDR2’s rated speed is specified at 400 to 800 megabits per second (Mbps) whereas DDR3’s doubles that to 800 to 1600 Mbps.
This means that routing requirements for byte lane, clock, and address and command signals is extremely critical. For that high level of performance, tighter tolerances are demanded including tighter control of length-matching, crosstalk, and electromagnetic interference (EMI). As an example, data bits within a byte lane should be 10 mils, and between byte lanes it should be within half an inch.
Thanks to more advanced packaging, there are more power and ground balls on a DDR3 memory ball-grid array (BGA) package than on DDR2. This not only improves power delivery, but also helps to improve signal quality and reduce signal loops. With the increased number of ground and power connections, ground bounce and Vcc SAG (signal after ground) are reduced. Ground bounce occurs on the ground pin, while Vcc SAG happens on the power pin. Both can occur when there are high inductance connections from the chip to ground, thus causing a spike on the reference planes when the signal switches.
Another plus is that the advanced BGA has two features that provides greater reliability. First, it has more balls and is fully populated. Second, improved I/O pin placement produces less skew between the BGA ball and inside wire bond distances and thus provides tighter timing of critical signals
Finally, as discussed earlier, DDDR3 comes with the fly-by termination scheme versus DDR2’s parallel termination. Fly-by provides a much higher level of signal integrity; and the eye diagram is more controlled. Fly-by also reduces stubs on the termination, resulting in better signal integrity on critical signals. Figure 2 shows the fly-by termination topology.
Because DDR3’s fly-by termination is used with clocks and command and address bus signals, it reduces simultaneous switching noise (SSN) by deliberately causing flight-time skew between the data and strobes at every DRAM as the clock, address, and command signals traverse the dual-in line memory module (DIMM).
DDR3 PCB routing considerations
The PCB and/or embedded system designer needs to take these new advances into account when routing DDR3 signals on the PCB.
Vrefor reference voltage is more important for DDR3 than it was forDDR2. Primarily, Vref should be isolated from noisy signals likeclocks. Vref should also be decoupled with a 0.1 microfarad (µF)capacitor very close to the power pin. This helps to filter some of thenoise.
The Vref POD should be a low inductance “thick”signal. It should be routed more densely than other signals, typically20 to 25 mils. Adequate current for Vrefs must be ensured and the tracemust be thick enough so it performs well and can supply minimal currentthat the system requires. Here, lower impedance also reduces intrinsicsignal noise. An unhindered reference plane is required for Vref, tokeep it quiet.
Once Vref is properly dealt with, a good referenceplane needs to be provided to all other signals, including DDR bits andcommand, control, at address lines, and clocks. A good reference planemeans less noise and crosstalk between those signal lines.
Datatiming or tuning is a third item that needs close attention. So, withindata byte lanes, the data bits should be length-matched to +/-10 mils.The higher the DDR3 frequency, the better controlled the timingtolerances have to be.
Next on the routing plan is the propertermination of the address, command, control lines, and clocksignals. Proper termination of address and command and control linesmeans selecting the correct resistor values for a pre-determinedtermination scheme, and then routing them correctly.
Whilerouting these signals, it’s important to use the JEDEC routing topologyfor DDR (http://en.wikipedia.org/wiki/DDR_SDRAM). (In fact, it’s a goodidea to keep notes on all JEDEC standards while working on a layout thatincorporates DDR2 and DDR3). Once address lines are routed, unusedaddress lines should be disabled so they do not act as antennas.
Finally,while routing DDR3 signals, the designer has to make sure all lines aretestable, whether they are byte lanes, address lines, or lines forcommand, control, and clocks. The goal is to have more than 90% testcoverage. Ideally, there should be at least one test point per line toproperly test the PCB.
Figure3: A calculated length of transmission line, called a stub, is createdto match impedance in transmission lines if a trace is not run throughthe test point.
Ideally a test point should be asmall pad that introduces minimum impedance discontinuity. A majorprecaution is not to have large test points, keeping them as small aspossible to avoid discontinuities introduced into a signal. This isespecially important if it’s an ultra-high speed signal. This alsoapplies to clocks or data lines to avoid signal ringing and reflection.
DDR4brings along its own set of considerations based on its advances. Takefor example a comparison between a layout based on DDR3’s 1600 megabitsper second (Mbps) and one based again on 1600 Mbps, but DDR4 is used. Inthis case, routing requirements are eased rather than increased becauseof DDR4’s new point-to-point architecture.
As a result, timingis eased, and routing is easier. But since speed and bandwidth areramped up to 3200 mega transfers per second for DDR4, then tightertiming comes into play.
There are two major advantages of DDR4as compared to DDR3: power consumption and performance, andlength-matching and on-die termination (ODT).
DDR4 will likelyconsume 30 to 40 percent less power than DDR3 since DDR4 will run at 1.2volts versus DDR3’s 1.5 volts. Also, DDR4 will be 1.7 times faster thanDDR3: a maximum of 3200 Mbps, double the speed of DDR3. Contributing tothe performance boost are more signal pins, DDR4 packaging will have284 pins versus 240 pins for DDR3.
Both the lower power andenhanced speed are due to the new point-to-point architecture DDR4 willbe sporting. The earlier DIMMs used a multi-drop bus. The point-to-pointarchitecture delivers better timing margins, handing the designer awider range of tolerances to work when performing the routing and lengthmatching of the different bits, clock, and address lines.
Length-matchingwill be slightly easier with DDR4 than with DDR3. However, this comeswith an important caveat at higher data rates. When DDR4 is operating ator near DDR3 data rates of 1600 Mbps, timing margins will remain thesame as for DDR3. But at DDR4’s peak performance rate of 3200 Mbps,tighter timing is required.
On-die termination( ODT) was arequirement for DDR3, but for DDR4, it’s not needed, allowing non-ODTrouting on point-to-point applications.
DDR3 – DDR4 similarities and differences
ForDDR4, a pseudo-open drain (PDO) I/O architecture will be used. Unlikethe traditional multi-drop bus interface used for previous DDRs, it hasmore relaxed timing margins and less power consumption than DDR3. Basically, it allows the designer to relax rules and achieve the sametransfer rates as DDR3.
Improved transfer rate, data rates, andspeeds are a given when the designer shifts from DDR3 to DDR4. Whilethe routing guidelines will be the same for DDR4 as DDR3, the memoryinterface will be more efficient, more powerful, and will have a muchbetter data rate: about 1.7 times faster than DDR3 with the same routingrules.
The DDR4 POD I/O structure adopts a fly-by terminationscheme topology, which worked extremely well with DDR3. The shift fromDDR2 to DDR3, was an evolutionary change as it relates to speeds androuting guidelines requiring PCB design changes. But going from DDR3 toDDR4 does not discernibly change routing guidelines compared to goingfrom DDR2 to DDR3.
DDR4 will require the same design rules asultra-high-speed designs using high speed SERDES logic. While placingtest points, it’s critical not to have signals close together, otherwisethe issue of crosstalk arises. For example, recommended spacing betweencritical signals should be five times the trace width they travel on toavoid crosstalk.
DDR4 is fairly new, butas more PCB designs are built and tested using DDR4, we will need toupdate our layout rules and strategies so that products perform asintended and there are no latent failures.
Syed Wasif Ali is an advanced certified designer (CID+) and a layout engineer atNexLogic Technologies, Inc., San Jose, CA. He received his BSEE fromN.E.D. University of Engineering and Technology in Karachi Pakistan.