The MIPI Alliance today introduced its new MIPI C-PHY specification, a physical layer interface for camera and display applications.
The alliance has also released updates to the MIPI specification's D-PHY and MIPI M-PHY physical layer technologies.
The C-Phy specification expands the MIPI Alliance’s family of physical layer specifications, broadening the variety of interface choices available to manufacturers and opening up new opportunities for companies to differentiate their product designs based on business-specific strategies or technology requirements.
Joel Huloux, chairman of the board of MIPI Alliance said the new C-PHY spec, released as v1.0, is designed to connect camera and display modules to an application processor. The interface allows system designers to easily scale the existing MIPI Alliance Camera Serial Interface (CSI-2) and Display Interface (MIPI DSI) ecosystems to support higher resolution image sensors and displays while at the same time keeping power consumption low.
“It also supports soft configurability of lanes within a link to optimize bandwidth and minimize pin count,” he said. “MIPI C-PHY can be implemented with MIPI D-PHY on the same device pins, which allows connections to the companion device with either PHY technology.
According to Rick Wietfeldt, chair of the MIPI Alliance Technical Steering Group, the MIPI C-PHY specification was developed to reduce the interface signaling rate to enable a wide range of high-performance and cost-optimized applications, such as very low-cost, low-resolution image sensors; sensors offering up to 60 megapixels; and even 4K display panels.
“MIPI C-PHY accomplishes this by departing from the conventional differential signaling technique on two-wire lanes and introducing 3-phase symbol encoding of about 2.28 bits per symbol to transmit data symbols on 3-wire lanes, or 'trios' where each trio includes an embedded clock,” he said. “Three trios operating at the MIPI C-PHY v1.0 rate of 2.5 Gsym/s achieve a peak bandwidth of 2.5 Gsym/s times 2.28 bits/symbol, or about 17.1 Gbps over a 9 -wire interface that can be shared, if desired, with the MIPI D-PHY interface.
Huloux said the MIPI Alliance also updated its MIPI D-PHY and MIPI M-PHY physical layer technologies. The updated MIPI D-PHY specification, v1.2, introduces lane-based data skew control in the receiver to achieve a peak transmission rate of 2.5 Gbps/lane or 10 Gbps over 4 lanes, compared to the v1.1 peak transmission rate of 1.5 Gbps/lane or 6 Gbps over 4 lanes. The MIPI M-PHY v3.1 specification introduces transmitter equalization to improve support for challenging channels while maintaining the peak transmission rate of 5.8 Gbps/lane or 23.2 Gbps over 4 lanes, which was achieved in its v3.0 specification.
“The MIPI Alliance’s three physical layers, combined with MIPI Alliance application protocols, address the evolving interface needs of the entire mobile device,”aid Ken Drottar, chair of the MIPI Alliance PHY Working Group. “Fundamentally, MIPI Alliance interfaces enable manufacturers to simplify the design process, reduce costs, create economies of scale and shorten time-to-market.”
The MIPI Alliance’s family of specialized physical layers supports a variety of mobile device protocols for chip-to-chip, camera and display applications that require high-performance, low-power serial interfaces and produce very low electromagnetic interference (EMI).
Each of the physical layers offers unique advantages and features that collectively address the most essential functions needed in today’s smartphones, tablets and laptop computers. MIPI M-PHY, for example, provides a high-speed physical layer specification for data transmission in a mobile terminal, and MIPI D-PHY is widely used for camera and display applications.
Because mobile connectivity is increasingly finding its way into additional industries, Huloux said the MIPI Alliance is working cooperatively with other standards development organizations whose technologies can use or benefit from MIPI interfaces.
“For example, MIPI M-PHY has been adopted as the physical layer technology enabling popular PC protocols to operate in mobile terminals,” he said. “Some of these externally developed standards include Universal Flash Storage (UFS) from the JEDEC Solid State Technology Association; Mobile PCI Express (M-PCIe) from the PCI-SIG, and SuperSpeed USB Inter Chip (SSIC) from the USB 3.0 Promoters Group.
MIPI C-PHY v1.0, MIPI D-PHY v1.2 and MIPI M-PHY v3.1 are now available to MIPI Alliance members and can be downloaded from the member portal on the MIPI Alliance web site.
(The MIPI Alliance is holding its first meeting in China with an “Open Day” to be held on Thursday, October 9 at the Le Royal Meridien Hotel in Shanghai. The event will be free and open to preregistered industry representatives, non-members, MIPI Alliance Members, press and analysts. )