MIPs-based multiprocessor at 1GHz - Embedded.com

MIPs-based multiprocessor at 1GHz

PMC-Sierra is sampling the integrated RM9000x2 64bit MIPS-baseddual processor which is manufactured in a 0.13µm, low-k copperprocess and runs the Linux operating system at 1.0GHz. It requiresless than 10W of total device power with each processor running at1GHz and all of the memory and I/O interfaces running at maximumfrequency.

The RM9000x2 integrates multiple high-speed bus interfaces, whichinclude HyperTransport, DDR SDRAM, SysAD and a boot bus, to enablelow latency access to main memory and high bandwidth to external I/Odevices – see figure 1. The RM9000x2 targets high-touch,performance-driven applications such as edge routers, DSLAMs andwireless base stations.

Fig 1: The RM9000x2 high speed interfaces to externalI/O

The RM9000x2 CPU subsystem consists of two E9000 MIPS-64instruction set compatible cores, both running at 1GHz. Each core hasan optimised cache architecture of high performance L1 data andinstruction caches, tightly coupled with 256Kbyte of joint L2 cacheproviding a total of 512Kbyte of coherent L2 cache.

The L1 caches are accessed in a single CPU cycle. Access to the L2cache is a 5 CPU cycles, or 5ns at 1GHz core frequency. The dualE9000 cores are connected to each other by a sophisticated processorswitch, which enables cache transfers between the CPUs at the corefrequency.

This high-performance architecture solves multiprocessing'sperennial problem of slow data transfers between processors in cachecoherent systems by delivering 64Gbit/s of inter-CPU bandwidth.

Cache coherency protocol

To accelerate the multiprocessing capabilities, a five-state cachecoherency protocol is used. The five-state MOESI protocol extends thefunctionality of the standard MESI protocol to permit one processorto access modified data from the other processor's cache. Fullhardware I/O coherency is supported over the HyperTransport and SysADinterfaces, enabling I/O devices coherent access to memory withoutsoftware intervention.

The dual CPU cores can run as fully cache coherent symmetricmulti-processors (SMP), or completely independent with hardwareenforced protection mechanisms. The latter mechanism might be usedfor separate control plane/data plane processing while the formermight be used for separate ingress/egress processing.

Packet processing

The RM9000x2 features multiple enhancements to its cachearchitecture that significantly increase packet-processingperformance.

Direct deposit cache provides the ability to write directly intocache over both the HyperTransport and SysAD busses, eliminatingcostly external memory cycles. In auto-deposit operation, the packetheader is automatically written into cache, while the payload iswritten into main memory. Live-Deposit operation provides the abilityto dynamically write entire HyperTransport packets into cache.

Live-deposit operation also supports writing directly into cacheusing direct memory access (DMA). Additional RM9000x2 cache featuresinclude Fast Packet Cache, which allows bypassing of L2 cache on aper-page basis and further increases packet-processingperformance.

On-chip I/O busses

The integrated high-speed bus interfaces include HyperTransport,DDR SDRAM, SysAD, and a local bus, which provides a boot bus andconnectivity to slower speed devices. The RM9000x2 HyperTransport I/Ointerface is a 500MHz DDR bus that delivers 16Gbit/s of raw busbandwidth for maximum performance and provides connectivity to arange of high-speed networking peripherals.

The 200MHz DDR memory controller provides 25.6Gbit/s of memorybandwidth. Up to 4Gbytes of error correcting code (ECC) protectedmain memory can be addressed. The SysAD bus enables connectivity toall SysAD-based peripheral devices and delivers a seamless upgradepath for existing RM7000 family designs.

Published in Embedded Systems (Europe) November2002

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