Mixed-Signal = Analog + Digital, or is there more to it? - Embedded.com

Mixed-Signal = Analog + Digital, or is there more to it?

Mixed-signal applications are among the fastest growing market segments in the electronics and semiconductor industry. Examination of any recent device–like a smart cell phone, tablet computer, digital camera or 3D TV–reveals very high integration of analog and digital functionality at system, SoC and silicon levels.

Driven by growth opportunities in mobile communication, networking, power management, automotive, medical, imaging, safety and security applications, many silicon vendors are refocusing their business on RF, high-performance analog and mixed-signal designs

Recently, we outlined an EDA360 vision aimed at mobilizing the industry to find a new ways to address the disruptive transformation systems and semiconductor companies are undergoing.  In the vision, increasing the efficiency of mixed-signal design is identified as one of the key elements that can boost design productivity and profitability.

Higher integration, along with the migration to advanced process nodes, bring new challenges to mixed-signal design, particularly in the areas of analog-digital co-design, functional verification, test, abstraction and behavioral modeling, noise analysis, chip integration, signoff, IC-package co-design and design data management.

In addition to the many technical challenges, companies are also facing serious problems in managing available resources, developing necessary skills and improving collaboration among design teams, all of which impact productivity and predictability critical to the profitability of a mixed-signal project.

 

Figure 1: Contrast of traditional and modern mixed-signal design

Traditionally, analog and digital design skills were separate, highly specialized disciplines, and success of a mixed-signal design project depended on the clear handoff among analog and digital teams. Meeting block-level specification usually ensured successful integration. Mixed-signal was indeed equal to analog plus digital.

In contrast, a modern mixed-signal SoC integrates a dozen or more mixed-signal blocks or IP components, each containing a hierarchy of tightly integrated analog and digital circuits.

Some mixed-signal IP blocks are reused, some designed concurrently and others acquired from third parties. Not just one analog and one digital, but multiple design teams are involved with many mutual dependences, each critical to the success of the overall project.

To realize such designs in a shorter development cycle and meet productivity and quality goals, cross-pollination of existing skills and the development of new skills, are required along with much stronger collaboration among design teams.

 

Figure 2: Organization of mixed-signal teams and their dependences

Functionally verifying mixed-signal designs is one of the top challenges. The traditional simulation method is becoming a bottleneck for complex mixed-signal IP blocks and even more so for SoCs, despite significant improvements in speed and capacity of transistor, RTL/gate and mixed-mode simulators. In addition to further simulation performance improvements, adoption of a model-based, metrics-driven verification methodology is required.

On the digital side, verification is established as a function independent from logic design, and digital verification teams are formed in most companies to develop test for adequate coverage to make sure the logic functions properly.

Analog designers rely on pure transistor-level simulation and their experience. Due to tight integration and strong interaction between analog and digital circuits in a mixed-signal design, it is no longer sufficient to verify them independently, and mixed-signal verification is required. 

A new discipline, ”mixed-signal verification” is emerging, requiring skills in mixed-mode simulation, behavioral model generation and characterization and test bench development. Mixed-signal verification engineers have a sufficient understanding of device physics and analog circuits, can write code and models (which most analog designers are reluctant to do), and verify mixed-signal designs all the while working closely with, but independent of, analog and digital designers through the entire design process.

Today, almost every analog block contains digital logic, and the size of the logic continues to grow. This is due to the digitization of analog functions or the introduction of digital controls in analog for flexibility, performance tuning, and area and power saving.

Furthermore, standard cell digital enables higher automation in layout generation. Analog layout designers have been creating layout for digital logic using interactive analog-centric flows, either as custom digital or incorporating small number of standard cells into analog layout.

This methodology is no longer productive due to an increase in the logic gate count. Layout designers need to make a choice to either:

a) Learn both analog and digital layout techniques and become a mixed-signal layout designer or,

b)  Outsource digital layout to another group within or outside the company or

c)  Establish close collaboration among analog and dedicated digital layout     designers to perform layout concurrently.

Each choice has advantages and disadvantages, with detailed analysis beyond the scope of this article. In short, some analog layout designers will become fluent in digital layout as well.  This is happening in small design companies, often out of necessity and more as the exception rather than the rule.

The outsourcing option is a good choice when digital layout is only occasionally needed. To ensure success of the project, someone on the analog team needs to be familiar with digital layout to be able to offload the task, verify and integrate the digital layout and manage changes.

The most challenging and the most promising option is the third: close collaboration. It requires two components, an integrated flow and a collaborative operational model. An integrated flow–with a unified database, technology and library setup, shared design intent, constraints and verification engines–enables analog and digital designers to closely collaborate on creating layout without the unnecessary overhead of data translation and information loss in rigid handoffs between them.

Design teams need to be committed to sharing responsibility for the entire project instead of owning just the analog or digital piece of it. For example, decisions on allocating and minimizing area or performing ECO need to be made jointly from a mixed-signal design perspective, instead of one team imposing its decision on the other. This approach results in higher quality designs achieved in shorter time and with fewer iterations among design teams.

Chip planning and integration requires skills different from those used for traditional specialized analog or digital design. A ”mixed-signal architect and integrator” need to understand how a chip interacts with the package and system.

The architect must be able to architect a chip to meet multiple objectives, such as minimal area and power; optimal placement of mixed-signal blocks with respect to top level routing, coupling noise and power distribution; The integrator must then integrate the chip to meet performance specifications that ensure full chip signoff for both analog and digital functionality. Neither specialized analog nor digital skills alone can cover this since a broader knowledge of both domains is required.

In summary, to meet the increasing complexity and challenges in mixed-signal chips, designers need to adopt tools and methodologies for higher automation, cross-pollinate analog and digital skills, develop mixed-signal experts able to bridge analog and digital domains, particularly in verification, chip planning and integration, and establish close collaboration between analog and digital layout designers to foster more concurrent creation of mixed-signal layout.

Enhanced support for real-number modeling and simulation lets designers incorporate analog and mixed-signal blocks in SoC verification without sacrificing performance.  With integrated extraction, timing and power analysis tools designers can confidently sign off on full-chip performance covering both analog and digital domains.

Mladen Nizic is Engineering Director, Solutions Marketing, at Cadence Design Systems.

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