AccelChip's 2005.3 version of its DSP synthesis and intellectual property (IP) toolkits for model-based design are aimed at digital signal processing (DSP) applications. New to the synthesis tool is a feature that allows for pipe-line insertion to increase design performance while lowering chip power. The company has also added enhancements to the tool's automated floating-point to fixed-point conversion utility that improves fixed-point simulation performance up to 100%. In addition, updates have been made to all third-party tool integrations to ensure interoperability.
To provide DSP algorithm and hardware developers with a compressive and verified model-based design flow from Matlab to silicon, partnerships with EDA and FPGA vendors provide an integrated DSP design environment. The 2005.3 release of AccelChip DSP Synthesis is certified to support the most current production version of Aldec Riviera, Altera Corporation’s Quartus II development software, Cadence NC-Verilog and NC-VHDL, Mentor Graphics ModelSim, LeonardoSpectrum and Precision RTL Synthesis, Synplicity Synplify Pro, Synopsis Design Complier and Design Complier FPGA, The MathWorks MATLAB and Simulink, and Xilinx ISE and System Generator for DSP. For more information, visit www.accelchip.com.