At the University of New Hampshire InterOperability Laboratory (UNH-IOL), we are fortunate to be able to follow technology developments in a number of areas, and watch as they go from sketches on a whiteboard to actual shipping products.
Sometimes these developments happen in their own bubbles, other times there are not so coincidental coincidences, where several industries are able to take advantage of technology originally developed for one community. We may be watching that happen right now as technologies originally developed for mobile are finding application in storage, and vice versa.
Mobile device makers tend to highlight high storage capacities of their devices. Lower end devices are typically in the 8-16 GB range, whereas higher end devices can have 128 GB or more. Most Android devices accept microSD cards, increasing their capacity further (currently microSD cards max out at 128 GB). But what are the technologies behind all this storage, and what’s in store for them and the future of mobile storage?
Today’s dominant mobile storage technologies
Today the dominant technologies for mobile storage are eMMC and microSD cards. Internal (i.e. non-user serviceable) storage is typically eMMC. Swappable and upgradeable microSD is what we know from use in cameras, phones, etc. The speed class on microSD refers to the read/write performance. The typical standard today is Class 10. Soon UHS (Ultra High Speed) cards will be available. Here are the key differences between eMMC and microSD:
Embedded, not upgradeable
10 MB/s Class 10, up to 312 MB/s for future UHS cards
Easily swappable, upgradable
Most users don’t think about the differences between these technologies. But when we look at the performance expectations on mobile devices, it’s worth asking if these technologies can handle the coming performance demands for mobile devices.
What are these performance demands? Stepping through an example may be helpful. Consider a 4K mobile display operating at 60 frames per second (fps). How much bandwidth will it need?
Here’s a simplified rough calculation:
4096x 2160 = 8847360 pixels
24 bits per pixel x 8847360 = 212336640 bits per frame
60 frames per second x 212336640 = 12,700,000,000 bits per second
12,700,000,000 bits per second = 1,590,0000,000 bytes per second
That's 1.59 GB per second, nearly 4 times the throughput available from eMMC today.
To be fair, we have greatly simplified the process that a system architect would go through to determine the necessary bandwidth. You can argue whether this simplification is valid or not, but we’re not trying to show how to build such a system, simply that existing technologies are at best being stretched to enable the demanded user experience and price point, and at worst, cannot meet the demand.
It’s important to keep in mind that system designers are juggling many competing factors, and we’ve ignored the effects of compression and buffering that can be used to save bandwidth and system cost. Architects will employ combinations of high performance (but constantly powered) DDR3 RAM, on board NAND Flash, and image processing and compression hardware to enable the best performance with minimal power draw. Surely a system with a lot of RAM could meet the necessary performance specs. But it would also have constant power draw and far exceed the sub $100 BoM of many devices. An expensive mobile device capable of showing a 4K movie is of little use if the battery dies at the climax of the movie.
The point is, today’s technologies aren’t enough. We need to ask what the new technologies are that will address this need. Is there one clear winner or will new technologies provide mobile device integrators and designers with more choice? Evolutions of technologies like NVMe, PCIe, UFS, and M-PHY (Figure 1 ) may lead to drastic performance increases for on-device storage. Each of these and how they can be used are examined below.
NVMe / PCIe / mPCIe
NVMe is a protocol for interfacing withsolid state drives (SSDs) over the PCIe bus. Existing PC drivers allowthese NVMe devices to look like hard disk drives to a PC operatingsystem, but with exceptional performance. Already NVMe devices areappearing in enterprise environments and so-called ‘all flash arrays.’As you would expect, the cost/GB of NVMe is high relative to HDD, butthat gap is narrowing quickly. Enterprise installations demanding highperformance are ready and willing to absorb the increased cost/GB ofNVMe SSDs and take advantage of their performance benefits. In fact,many large enterprises see savings on cooling and power when switchingto all flash arrays and all flash data centers, making that choice evenmore compelling. Even though the enterprise is where NVMe is having anearly impact, it’s a stated goal of the technology to migrate into theclient space as well.
What is the client space? Desktops,workstations, laptops? These types of devices already have PCIeinterfaces in them and can easily handle the standard 2.5” disk driveform factor that many early NVMe devices use. What about convertibles?Tablets? Phones? Yes, especially with the introduction of the M.2 formfactor. This further reduces the space that storage will occupy in adevice. Furthering the mPCIe interface could potentially enable the useof PCIe storage over a phy specifically designed for low-power mobileapplications. In this case the ‘m’ stands for ‘mobile.’ It’s an adaptionof the PCIe protocol onto a low power phy, namely M-PHY (more below).Remember, PCIe was initially developed as a high performance interfacefor the PC and server worlds, where power wasn’t a major concern. Theneed for a new phy stems from the need to have a low-power interface,hence M-PHY.
UFS / UniPro
UFS (Universal FlashStorage) is a protocol created by the JEDEC Mobile Forum (the samepeople that brought you DDR and MMC). While still a future technology,UFS is designed to be implemented in either an SD card or embedded chipform factor. The UFS protocol will use the MIPI UniPro protocol as itstransport. This is important on several fronts. Having theimplementation defined for multiple form factors enables design reuse.This speeds up development and drives down cost. Using UniPro may leadto design reuse as well. Within the MIPI Alliance, UniPro is targeted tobe used as a transport for camera interfaces as well. Reusing thetechnology on multiple interfaces within a mobile device further speedsup development and drives down cost. UniPro is also designed to use thatlow-power electrical layer, M-PHY.
M-PHY isthe technology that serves as the foundation for the coming performanceboost in mobile storage. The M-PHY specification created by the MIPIAlliance allows low power transfers of up to 5.8 Gbps per lane, andmulti-lane systems are defined. Future specification releases will pushtransfer rates even higher. The leading processor companies in both themobile and PC arenas are key supporters of the work of MIPI Alliance, sowe can expect to see M-PHY interfaces in the near future. But when?Economics will decide: when the current crop of interfaces becomes cheapenough that it’s economically viable to move to a newer, more expensiveinterface that enables a new set of experiences.
We can’t fullypredict the types of architectures that future mobile and storageproducts will have. Most companies have roadmaps stretching years intothe future. However, the possibilities enabled by technologies underdevelopment today are exciting, and no doubt there are forthcomingapplications we haven’t even yet considered.
David Woolf manages the Storage and Mobile Consortia at the University of New Hampshire InterOperability Laboratory (UNH-IOL). He has developed dozens of industry-reviewed test proceduresand implementations as part of the team that has grown the UNH-IOL intoa world-class center for interoperability and conformance testing.David has also helped to organize numerous industry interoperabilitytest events at both at the UNH-IOL facility and off-site locations. Hehas been an active participant in a number of industry forums andcommittees addressing conformance and interoperability, including theSAS Plugfest Committee, SATA-IO Logo Workgroup, co-chair of the MIPIAlliance Testing Workgroup, and coordinating the NVMe Integrators Listand plugfests.