VULCANmachines, has released it second-generation processor for Java-based technology. Moon2 is a 32bit microprocessor core designed for use in highperformance, low-power, Java-based embedded systems. The processor is available as Soft IP to be licensed and synthesized into ASIC and FPGA based system-on-chip designs.
It is a native processor using a stack-based architecture designed from the ground up to execute Java bytecodes optimally. Bytecodes are executed directly, with the core of the instruction set implemented in hardware, and complex tasks microcoded or delegated to firmware.
By eliminating the software overhead of a Java Virtual Machine or JIT solution, Moon2 gives an order of magnitude performance increase in Java execution.Moon2 can be employed as a coprocessor to a host core in a multi-lingual, multi-processor system. For example, where a heritage design has significant investment in existing code (which may be written in C or assembler), it can be used to accelerate the execution of Java without subtracting from the processing bandwidth of the host core. Alternatively, where there is no significant legacy code Moon2 can be deployed as a stand-alone processor in single language (i.e. Java) system.
Both VHDL and Verilog implementations available and its uses 27K gates plus 3K ROM and 1K single port RAM. Power consumption is typically 0.25mWMHz in 0.18mm process.
There are interfaces to all major industry standard bus architecture and an optional code cache. The physical device access is in Java with no operating system or Virtual Machine required.
The runtime environment is designed to support the J2ME CLDC specification and beyondMoon2 comprises an instruction execution unit and a datapath unit, which handles ALU operations and stack and memory access.
The instruction execution unit fetches bytecodes from the memory location pointed to by the program counter, typically fetching more than one complete bytecode at a time since the width of the data bus is larger than most bytecode sequences.
The optional code cache in Moon2 can be used to decrease the execution time of frequently used code. Furthermore the cache minimises bus contention and memory access times where it is deployed as a slave to a host processor. Bytecodes are stored in a small prefetch buffer. Since this buffer can hold several memory words at once, bytecode execution can usually be performed at a rate of one bytecode per clock tick.
In cases where a particular bytecode requires multiple ALU operations, several microcode instructions are executed preceding the next bytecode fetch. The current bytecode is decoded by a microcode ROM which indicates, for example; the ALU operation required and the size of immediate arguments.
The datapath unit consists of the ALU, hardware stack, and a number of internal registers. The hardware stack is implemented in memory on the device upon which the Moon Core itself is implemented. In general ALU operations are executed on the top two elements of the stack; also data may be pushed onto the stack (e.g. by an immediate data instruction), or popped from it (e.g.as the result of a two-operand operation). The pushes and pops required for stack operations are merged together wherever possible.
A generic bus architecture is used to simplify the integration of third-party IP with the Moon2 Core. Simple HDL wrappers are available to enable IP which is compliant with industry standard bus architectures such as AMBA AHB or PVCI (Peripheral Virtual Component Interface) to interface directly to Moon2.
Kit aids development of Moon2-based designs
Vulcan Machines has also developed the MoonLander development kit which provides an implementation of Moon2 as a stand-alone processor core. Based on Altera's SOPC development board, MoonLander forms a system prototyping tool for Java embedded system designers enabling both hardware and software integration and verification.
The Moon2 reference design is pre-loaded into flash memory on the MoonLander board and boots up on power up. Altera's Quartus II software can be used to re-program flash memory using a Programmer Object File (.pof), alternatively the PLD itself can be programmed directly with a bitstream (eg .sof) file via a MasterBlaster or ByteBlaster programming cable.
The reference design includes a number of peripherals including a UART, external SDRAM memory interface, LED interface and a JTAG port to enable debug and code download.
HDL source code for the reference design is provided, along with a HDL simulation test bench which mimics the operation of the MoonLander development board. The development board includes an APEX 20K400E device, which is 22% utilised with the Moon2 reference design, 4Mbyte of Flash memory, pre-configured with the 32bit Moon2 reference design, and 64Mbyte SDRAM module in a DIMM socket.
It has standard interconnects for 10/100 Ethernet, (USB) and Firewire as well as two RS-232 serial ports and two PS/2 ports. Debugging ports, including the SignalTap embedded logic analyser and JTAG. Multiple clocks, user configurable I/O lines, switches and LED's are provided.