More about designing with Embedded DSPs

For your convenience, collected here is an archive of  Design and Product How-To articles that have been posted on line at EET/ about designing with Digital Signal Processors (DSPs).  For broader issues relating to algorithm development and implementation in hardware or software, you should also check out theEET/Signal Processing DesignLine. I am constantly updating this list, so check back occasionally to see what's new:

DSP Tricks: Computing inverse FFTs using the forward FFT
Two neat ways to compute inverse Fast Fourier Transforms using the forward FFT algorithm.
DSP Tricks: Approximate envelope detection
Some useful tricks for computing approximate envelope detection, useful in estimating signal magnitudes in automatic gain control.
DSP options to accelerate your DSP+FPGA design
Before embarking on a high-performance DSP system design, it would pay to evaluate the DSP solutions portfolio offered by the different silicon vendors. This article explores some typical DSP solutions.
How to achieve 1 trillion floating-point operations-per-second in an FPGA
ed on recent technological developments, high-performance floating-point signal processing can, for the very first time, be easily achieved using FPGAs.
The basics of DSP for use in intelligent sensor applications
In this three part series, the basic framework is described for using digital signal processing in analyzing and processing analog data gathered by intelligent sensors. Part 1: Foundational DSP concepts.
Digital Lowpass: A filter by any other name is still a filter
Understand the realization of an analog filter in digital domain, using an FPGA
The Need for Variable Precision DSP Architecture
FPGAs with variable-precision DSP block architecture are the only programmable devices that can efficiently support many different precision levels including floating-point implementations. This DSP architecture enables the next-generation of high-precision and high-performance signal processing applications. spacer
Increasing bandwidth in industrial applications with FPGA co-processors
This article discusses the general issues of moving part, or all, of a DSP industrial application onto an FPGA using system software design tools. Using an FPGA and automated design software, design engineers have the ability to optimize system performance in ways not possible with a traditional DSP.

spacerUsing a scheduled cache model to reduce memory latencies in multicore DSP designs
Freescale engineers describe a new software mechanism ” the scheduled cache model ” and the supporting hardware that reduce the need for DMA programming and synchronization to achieve high core utilization, relying on hardware mechanisms (some controlled by software) to increase cache efficiency.
spacerAnalysis of Microchip's PIC32 library
With the 32-bit MIPS 4K core, Microchip is now competing with the ARM juggernaut so offering optimized DSP libraries for the PIC32 is a good strategy. BDTI's Jeff Bier examines the library, in particular he looks at how it stacks up against ST Micro's ARM Cortex-M3-based STM32 library offering.
spacerFloating a new (DSP) idea
Floating point (FP) DSP architectures have been around for a long time and are notable for their raw performance versus fixed point. However, TI Principal Fellow Gene Frantz 'floats' the possibility of a new architecture that could quadruple a floating pointer's performance. What do you think?
spacerPRODUCT HOW-TO: Complex matrix inversion on the StarCore SC3850 DSP
Complex matrix inversion is used in LTE, WiMAX, and other communication applications. Here's how to do efficient 4×4 complex matrix inversion on the StarCore SC3850. Source code and a MATLAB reference model are included.
spacerPRODUCT HOW-TO: DSP/FPGA platform for video surveillance
Avnet's video surveillance platform pairs a TI DM6437 DaVinci DSP with a Xilinx Spartan-3A DSP FPGA. here's how the platform works, and how to get the most out of it.
Analysis: ST's low-cost MCU gets DSP software
BDTI examines ST's new library of DSP software for its low-cost ARM microcontroller, the STM32. The library includes a speech codec, FIR and IIR filters, a PID controller, and an FFT.

DSP Tricks:  Frequency translation using decimation
Here is a tip on how to do freguency translation using decimation.
Analyzing DSP networks with Mason's Rule
Here is an easy way to obtain the z-domain transfer function of a DSP network (DSP block diagram)
The math of DSP: Part 5 – Orthogonality
Explained is the concept of orthogonality and the concept of quadrature signals is introduced.
The math of DSP: Part 4 – Convolution, Fourier and Nyquist
Explained are the details of convolution and Fourier series calculations and the Nyquist sampling theorem
The math of DSP: Part 3 – Filters
The basics of low-pass and high-pass filsters and an explanation of the concept of causeality.
DSP Tricks: DC removal
Some tips on block data DC removal, real time DC removal and real time DC removal with quantization.
The math of DSP: Part 2 – Complex numbers
Topics covered are real and imaginary numbers, periodic signals, digital frequencies and discret arithmetic.
The math of DSP: Part 1 – Series, integration and frequency
The basic math for DSP, including polynomials, transcendentals, series, limits, integration, polar notation and frequency.
DSP Tricks: Efficient polynomial evaluation
Here are some tips on on efficial polynomial evaluation
Analysis: Freescale's six-core DSP
BDTI examines Freescale's new six-core DSP chip, the MSC8156, which targets wireless base stations.
Combining DSP and MCU operations in computationally complex time-critical apps
A Product How-To on using the Fujitsu 91470 MCU/DSP combo for digital filter apps that evaluate systems states and carry out fast loops
What's your sine?
A new approach to direct digital frequency uses a combination of lookup tables and trig identities that lends itself to more efficient implementation on DSPs.
DSP Tricks: Smoothing impulsive noise
Some tips on smoothing impulsive noise by using a technique originally used to detect microampere changes in milliampere signals.
Optimizing video analytics on a DSP
Here's how to implement both video compression and analytics on a single DSP. Topics covered include algorithm, memory and code optimization.
Speeding up the CORDIC algprothm with a DSP
When a CORDIC algorithm is implemented on a DSP, can the multipliers improve CORDIC performance?
DSP Tricks: Interpolating a bandpass filter
Some tips on interpolating a bandpass signal
Architecture oriented C optimization techniques: Part 2 – Memory and more
How to optimize C for memory alignment, cache features, endianness and application specific instructions.
Architecture oriented C optimization techniques: Part 1 – DSP features
Here is how C optimizations can take advantage of zero overhead loop mechanisms, hardware saturation, modulo registers and more.
Implement dual OS signal processing with Linux and the DSP/BIOS RTOS
In mixed signal DSP/GPU environents use a system virtual machine to run both Linux and the DSP/BIOS RTOS concurrently on the same DSP processor.
DSP Tricks: Interpolating a bandpass signal
Some tips on the interpolation of a bandpass signal.
DSP Tricks: Spectral leak location algorithm
A useful way to estimate the frequency of a sinusoid or the center frequency of a very narrowband signal..
Using programmable logic for efficient and effective DSP design
With an FPGA front-end that allow access to the latest I/O technology, as well as  IP blocks for the latest standards, designers have flexibility to choose the right  interfaces without making changes to the DSP software.
Asynchonous DSPs: Low power, high performance
An acynchronous DSP offers better power, performance and reliability than one based on standard synchronous logic, enabling simpler and less expensive PCB and power supply design.
DSP system design: Part 2 – Critical design choices
How to choose hardware and software architectures, how to choose an RTOS and how algorith and I/O libraries impact the development process.
DSP system design: Part 1 – The basic laws
Ten laws that yout can use to guide DSP system developing including such topics as economies of scale and experience effect, DSPs vs. FPGAs, fixed- vs. floating-point and RTOSes and algorithm libraries.
Signal processing on the MIPS 74K
BDTI evaluates the signal processing features of MIPS high performance superscalar core, the 74k.
DSPs versus FPGAs for multiprocessing
Here's whats available for high performance multiprocessor systems and how to make the best choice between DSP, FPGA or a hybrid of the two.
Avoiding noise and EMI problems in DSP systems
Noise and EMI can disrupt the operation of a DSP system or cause the design to fail FCC certificqtion. Here is how to avoid these problems with PCB layou and return path coupling.
Modulation roundup: error rates, noise and capacity
A comparison of various digital signal modulation schemes such as BPSK, QPSK, PAM, 16PSK, 32PSK, 16QAM and 64QAM using a variety of metrics.
DSP Tricks: Computing FFT twidle factors
Some useful tricks for computing Fast Fourier Transform twiddle factors.
DSP Tricks: Building a practical spectrum analyzer
Some tricks for implementing a spectrum analyzer by modifying the time-domain data before applying a radix-2 FFT algorithm.
Frequency domain toutorial: Part 2 – Complex signals and  spectral diagrams
Building on the basics introduced in Part 1, this article introduces the concept of quadrature (complex) signals and explains the nature and notation of the spectral diagrams used in DSP.
Freguency domain tutorial: Part 1 – Dealing with  ambiguity
What you need to know about the mathematics and notation of FFTs and the discrete frequency domain, starting with how to deal with discrete signal ambiguities.
Speaker equalization using FIR filters
Pros and cons of using FIR filters for speaker equalization versus DSP-, MCU- and FPGA-based approaches.
DSP Tricks: A/D conveter testing techniques and finding missing codes in ADCs
Some tricks for using DSP techniques to test A/D converters and some tips on how to detect missing codes in ADCs.
Symbol error rate for M-QAM modulation
Krishna Pillai shows how to calculate the error rate for modulation schemes such as QPSK, 16-QAM, 64-WAM and provides a MATLAB/Octave scripts for computing symbol error rate.
Making design choices between DSPs and FPGAs
Design guidelines on how to choose between DSPs and FPGAs or a combination of the two taking into account device cost, performance, NRE and availability of application-specific features.
Multirate DSP: Part 3 – ADC oversampling
The principles of oversampling in analog to digital converters and how to apply these to a signal-delta ADC.
Multirate DSP: Part 2 – Noninteger sampling facors
How to change the sampling rate by a noninteger factor as well as multistate decimation and polyphase filters as will as application of up/down sampling to a CD player application.
DSP Tricks: Reducing A/D converter quantization noise
How to use oversampling and dithering to reduce analog to digital conversion quantization noise.
Multirate DSP: Part 1 – Upsampling and downsampling
Part 1 introduces the concepts of multirate signal processing, explaining how to upsample and downsample by an integer factor. MATLAB code included.
How to implement DSP algorithms using the Spartan-3E FPGA starter board
This “How-to” is an excerpt from “Embedded Design using Programmable Gate Arrays”
2007 DSPTricks: Fast multiplication of complex numbers
Here is a quick and easy way to do fast multiplication of complexnumbers.
CombiningC code with assembly code in DSP applications
Here's how to integrate assembly code into C, including suchtopics as compiler conventions, inlining, intrinics, register bindingand debug strategies.
DigitalSignal Processing Tricks: High speed vector magnitude approximation.
Richard Lyons takes on high speed vector magnitude approximation inanother in an ongoing series of DSP design hints and tricks.
Ensuringhigh quality video communications
As the migraton to high definition picks up speed, video systemdesigners are facing new challenges relation to DSP bandwidthrequirements, image quality, transcoding and digital media codecflexibility.
Multichiparchitectures partition H.264 tasks for high quality video
For high quality video enconding, transcoding, transrating anddecoding, multiprocessing devices are necessary. Here are some tips ondistributing the tasks among multiple DSPs and FPGAs. 
Usingmixed signal DSPs in embedded controlapplications.
Dr. Finbarr Moynihan describes how changing demands for embeddedcontrol have lead to the development of single chip devices based oncore competencies in digital signal processing
 BDTIbenchmarks picoChip PC102
BDTA has released the first independent benchmark results comparingpicoChip's massively parallel PC102 chip to that of high performanceDSPs and FPGAs.
Fundamentalsof embedded video: Part 5
The final part in this series takes a look at a sample videoapplications, touching on the major DSP and processing blocks involved.
Fundamentalsof embedded video: Part 4
Part 4 in this series looks at video flows from a processor or DSPstandpoint, focusing on features that enable efficient datamanipiulation and movement.
Fundamentalsof embedded video: Part 3
Part 3 in this series looks at video flows from a system level,discusses the types of video sources and displays that compromise anembedded video application.
Fundamentalsof embedded video:  Part 2
Part 2 in this eries discusses color spaces and gamma correction andexplains the basics of digital video.
Fundamentalsof embedded video: Part 1
The first part in this series explains how video signals are tailoredto the human vision system and reviews the basics of NSTC and PAL videosignals.
InfrastructureDSPs for the triple play era
Emerging voice/data/media networks requre a combination of highperformance and high speed I/O Here's how to pick a DSP that will doall this and provide a cost effective solution as well.
Fundamentalsof embedded audio: Part 3
The final part in this series reviews data management schemes such asdouble buffering and DMA transfers and then discusses the basics ofaudio algorithms.
Fundamentalsof embedded audio: Part 2
Part 2 in this three part series discusses numeric formats as theyrelate to audio processing, with a focus on dynamic range and precision.
Fundamentalsof embedded audio: Part 1
Part 1 in this series explains how processors and DSPs interface withaudio signals with a focus on the basics of audio converters and commonperipheral standards for connecting these devices.
ADCsfor DSP Applications – Part 4
Part 4 in this series exampines jitter, delay and other  errors inADCs.
ADCsfor DSP Applications – Part 3
Part 3 in this series continues the discussion of sigma-delta ADCs witha loop at oversampling, bit scrambling and dynamic range.
ADCsfor DSP Applications – Part 2
Part 2 in this series explains how sigma-delta analog-digitalconverters work, covering quantization, noise shaping, and calculatingthe effective number of bits.
ADCsfor DSP Applications – Part 1
Part 1 of this five part series gives an overview of the most popularADCs for DSP: successive approximation, sigma-delta flash, subranging(or pipelined) and bit per stage (ripple).
Revisitinghomegeneous versus heterogeneous
Jeff Bier looks at the trade-offs in using homogeneous versusheterogeneous processing elements in multi-core chips for DSPapplications.
FFTconvolution and the overlap add method
For long filters, FFT convolution is faster than standard convolution.Here is how it works and how the overlap-add method plays a role.
DigitalSignal Processing Tricks – Frequency Translation without multiplication
Richard Lyons takes onfrequencytranslation withoutmultiplication in the first of an on-going series of DSP design hintsand tricks focused on creative techniques that professionals can use tomake their digital signal processing algorithms more efficient.
Topdown DSP design for FPGAs
High level C++ synthesis in combination with FPGAs is anattractive solution for achieving a rapid path from C++ to RTL runningin hardware.
Fundamentalsof embedded audio: Part 3
This part in a series on embedded audio reviews data managementschemes such as double buffering and DMA transfers and then discussesthe basics of audio algorithms.
Fundamentalsof embedded audio: Part 2
This part in a series on embedded audio algorithms discussesnumeric formats as they relate to audio processing, with a focus ondynamic range and precision.
Fundamentalsof embedded audio: Part 1
This first in a series on embedded audio algorithms explains howprocessors interface with audio signals as well as delves into thebasics of audio converters and the common peripheral standards forconnecting to these converters.
Ultra-low-powerDSP design
Here's how IMEC built a sub-100 uW DSP by tuning its algorithm,processor architecture and memory system, as well as through clockgating. The article presents detailed power results for eachoptimizaion.
DSPSilicon takes on many forms
Here's a guide to the chips used in signal processing: DSPs,MPUs, FPGAs, multiprocessors, massively parallel processors and more.
Usinga dual core DSP engine as a soft graphics renering accelerator
The principle reason for using a DSP instead of an externalHardware Graphics Accelerator lies in the significant cost savings.
Compileroptimization for DSP applications
Here's how to use compilation options to improive performance inDSP applications.
DSPserves the convergence needs of small businesses
For OEMs, selecting the right technology can make it easier toreach small and medium sized businesses with new devices for convergedvoice, video, and data services.
 Widebandvs narrowband VoIP codecs
Here's how wideband and narrowband G.7xxx codecs compare interms of voice quality, band width requirements and computationalloading.
Analysis:1 GHz MIPS core is DSP speed demon
The new MIPS 74L targets demanding applications like H.264.Here's how it works, and how it compares to the competition.
Implementingfloating point DSP on FPGAs
Here's how to use PicoBlaze processors for high performance,power-efficient floating point DSP.
DesigingFFTs for cache-based DSPs
Here's how to get the best FFT performance out of a chache-basedDSP.
Massivelyparallel processors for DSP, Part 1
In this two part series, BDTI explains why you should considermassively parallel processors and what to look like in these chips,looking at the inner workings of processors like IBM's Cell, Stretch'sreconfigurable cell and Mathstar's FPOA.
HowVideo Compression works
Explained here is how video codec software algorithms like MPGE-4 andH.262 work and how they differ as well as the demands they make ongeneral purposed and digital signal processors.
Analysis:How Tensilica's D1 video engine works
Tensilica's latest DSP-based video engine can do both H.264 and MPEG-4encoding at D1 resolution. BDTI explains how it works.
Analysis:CEVA's 32-bit, dual MAC Teaklite-III DSP
CEVA has soupted up its Teak core for audio and 3G applications. Here'show it works and how it compares to the competition.
DSCsfuel  the green revolution
Digital signal controllers are a new class of processor that combinesthe best attributes of micorocontrollers and digital signal processors.
Backto the basics: Tested and effective methods for speeding up DSPalgorithms
Inthis brief tutorial, Ninin Jain of Mindtree provides a wealth of usefultips on speeding up your DSP code and your application through bothsource and algorithm level optimizations.
Graphicalprogramming for DSPs
Graphical programming can help you reducetime to market, improve code reuse and port your design to multipleplatforms. Here's how.
Nextgeneration VoIP and the role of DSP
Emerging technologies such as highdefinition voice are expanding the role of the IP phone. Here's how tochoose a DSP platform that can keep up with the changes.
Analysis:Hypercore touts 256 CPUs per chip
Plurality's Hypercore supports up to 256 SPARC CPUs on a single IC.BDTI explains how it works and what it will take for the chp to succeed.
Multicoretrend a challenge to DSP vendors
There's been a lot of press about start-up companies offeringmulticore-DSP chips. What's less discussed is that DSP chip vendorshave been offering mult-core DSPs for some time.
DSPbenchmark bamboozles
The changes in signal processingapplications are making DSP vendors meet new demands while stilladdressing the old ones – or risk being marginalized in their ownmarkets.
Realtime operating systems for DSP, Part 8
In this final part in a series, you learn how to analyze systems withaperiodic tasks as well as understnd the dangers of priority inversionand how to avoid it using priority inheritance.
Realtime Operting systems for DSP, Part 7
Part 7 of this 8-part series shows how toanalyze scheduling behavior, and to ensure tasks meet their deadlines.It also shows how to account for interrupt latency and contextswitching overhead.
RealtimeOperating systems for DSP, Part 6.
Part 6 of this 8-part series reviewsvarious RTOS scheduleing algorithms – including both static and dynamicscheduling algorithms – and explains the pros and cons of each.
Equivalentresults: A methodology to measure the effects of high speed compression.
Real-world examples demo the benefits ofusing appropriate compression, such as lower pin counts, powerconsumption and system costs as well as reduced board area.
Analysis:BDTI releases ARM Cortex-A8 benchmarks
The Cortex-A8 achieves impressive performance in BDTI's video andsignal procesing benchmarks, about 2X the performance of an ARM11.
Analysis:Xilinx Spartan gets DSP
BDTI explains how the new Spartan FPGAsfrom Xilinx can offer substantial DSP performance at lower cost andcompares the new offering to its previous Virtex-4 and Virtex-5.
Real-TimeOperating Systems for DSP, Part 5
In Part 5, details are provided on how to protect critical code andresources using semaphores, spin locks and other techniques. Alsoexplained is how to synchronize independent tasks.
Real-TimeOperating Systems for DSP, Part 4
In this segment in an eight part series, Robert Oshana of TI shows howto detect and recover from a deadlock, how to avoid unsafe states andhow to avoid corruption of shared resources.
Selectingmemory controllers for DSP
Deepak Shankar of Mirabilis Design describes how to deal with latencyissues in systems where DSP performance is often limted by I/Oconstrants.
Real-TimeOperating Systems for DSP, Part 3
In this third of an eight part series, the focus is on the RTOS kerneland how it prioritizes tasks. Also explained are memory allocation,system calls and hardware concepts.
Asimple, efficient FFT implementation in C++, Part 1
This article, first in a series, describes a new efficientimplementation of the Cooley-Tukey fast Fourier Transform )FFT)algorithm using C++ template metaprogramming.
Real-TimeOperating Systems for DSP, Part 2
In the second part in this eight part series, Robert Oshana introducesthe concept of multitasking and how an RTOS schedules tasks forexecution.
Howto write an optimized FIR filter
A  brief tutorial on how to write optimized FIR filter code for aDSP, using the Texas Instruments C55x as an example.
Real-TimeOperatingSystems for DSP, Part 1
In the first in an eight part series,discussed are the basics of an RTOS and how to select one optimised forDSP, with a focus on the chip support library.
Testingand Debugging DSP systems, Part 6
The final part in this series reviews the common bugs found in DSPapplications and outlines different testing methods for finding thesebugs.
Comparingmainstream DSP processors: a survey
Analyzed are digital signal processors form Analog Devices, Freescaleand Texas Instruments including low cost fixed point, high performancefixed point and floating point DSPs.
Analysis:TI's DaVinci Evaluation Module
Here is an excerpt from a report that BDTI did based on its hands onevaluation of Texas Instrument's Digital Video Evaluation Module(DVEVM).
Analysis:Stretch's second gen configurable DSP engine
The S6000 is a RISC processor incorporating a configurable multicorecompute fabric of multiple DSP elements within its data path. Explainedhere is how it works and how it compares to more traditional processors.
ProgrammableDSP processors: Make them all, or one?
A pivotal question for the current crop of DSP and multicore startupsis whether to offer their processors as flexible general purpose chipsor as highly specialized, application specific designs.
Analysis:Stream Processors' data-parallel architecture
SPI's novel multicore 'stream processor' is derived from a researchproject at Stanford Univeristy. BDTI explains how it works.
Programand optimize DSP C code: Part 5
Part five of this five-part seriesshows how to optimize memory performance, and how to make speed vs.size tradeoffs.
Testingand Debugging DSP Systems, Part 5
Part five introduces the concepts of real-time data collection and datavisualization. It also explains how compiler options affect thedebugging process.
Testingand Debugging DSP Systems, Part 4
Part four explains how to use breakpoints, event triggers, and programtraces to debug code.
Programmingand optimizing C code, Part 4
Part 4 explains why it isimportant to optimize “control code,” and shows how to do so.
Testingand Debugging DSP Systems, Part 3
This article explains how emulation effectively imitates the DSPprocessor in its electrical characteristics and performance.
Programmingand optimizing DSP C code: Part 3.
Part 3 explains how to access DSP features like hardware loopsand circular addressing from portable C. It also shows how to usepragmas and inline assembly.
Programmingand optimizing DSP C code: Part 2
This second of a five-part series shows howto optimize DSP “kernels,” i.e., inner loops. It also shows how towrite fast floating-point and fractionalcode.
UseESL synthesis techniques to replace dedicated DSPs with FPGAs
If your application's not the most compute intensive, you mayfind that using an FPGA as a replacement for a dedicated DSP is a goodidea.
Howto use M and Simulink for DSP control and datapath design
This tutorial discusses the tradeoffs of abstraction versusimplementability and highlights an approach of embedding M intoSimulink to gain some of the advantages of both.
Analysis:BDTI certifies ARC's H.264 performance
BDTIhas certified the H.264 decode performance of the H.264 decodeperformance of the ARC video subsystem. In this article it reveals theperformance numbers and the test process behind them.
Testingand Debugging DSP Systems: Part 2
Part two of this six-part series explains the workings of theJTAG (IEEE 1149.1) boundary-scan technology. It defines the test pinsand the test process associated with a JTAG port.
Testingand Debugging DSP Systems, Part 1
Part one of this six-part series introduces the hardware usedfor debugging, the debugging challenges facing DSP programmers, anddebugging methodologies.
Programmingand optimizing DSP C code: Part 1
This first of a five-part series introducesthe basic principles of writing C code for a DSP processor. It alsoexplains how to profile and optimize code.
Designinga DSP-based Digitally Controlled DC-DC Switching Power Supply: Part 2
The second in a two part tutorial on DSP-based DC-DC digitalcontrol comparing two design methodologies: Direct Digital Design andDesign by Emulation.
DSPCompensation for Small Loudspeakers
Small loudspeakers and noisy listening environments ruin audioquality. Here's how psychoacoustic DSP-based algorithms can help.
Signalprocessing isn't a commodity
DSP functions are not interchangeable, and that means they wil notbecome commodties anytime soon.
Canthe ARM11 handle DSP?
Can ARM's latest core play the role of a DSP? Is it ready to take onvideo? BDTI's just-released benchmark results and analysis answer thesequestions.
Fixedvs. floating point: a surprisingly hard choice
Which is better: a fixed-point DSP or a floating-point DSP? Theanswer may surprise you–and so may the reasons. This article shows howto make the right choice, using two $5 DSPs as examples.
Designinga DSP-based Digitally Controlled DC-DC Switching Power Supply
Part 1 in a tutorial on DSP-based DC-DC digital controlcomparing two design methodologies: Direct Digital Design and Design byEmulation
Analysis:Freescale's dual core Audio DSPs
Freescale's latest audio processor is a dual core DSP packed withfeatures, targeting next generation DVD players and other high endapps. BDTI explains how it works, and how it stacks up against thecompetition.
Analysis:TI's three core 65 nm DSP
Texas Instruments' latest DSP is a three core chip targeting GSM,TD-SCDMA and WiMax base station applications. BDTI expains how it works.
FPGAsvs DSPs: A look at the unanswered questions
BDTI examines how FPGAs and DSPs compare in terms of performance, cost,power and ease of development.
Parallelprocessing for multi-core DSPs
With a dynamic scheduler, software developers can writeapplications that can scale in performance by running on an arbitrarynumber of DSP processors to achieve the desired performance, whileusing and sharing all processors efficiently.
DSP-basedsystem-on-chip moves speech recognition from the lab to portabledevices
Researchers from Tsinghua and Infineon Technologies describedevelopment of a speech recognition system-on-chip for use in consumerapplications such as toys, voice-based remote control and speechrecorders.
WhyMultiprocessor DSP Systems Need CORBA
CORBA enables software components in a multiprocessor system toeasily communicate–regardless of what language they are written in,what OS they run on, or where they are located. Even better, COBRAmakes it easy to move functionality between DSPs, GPPs, and FPGAs.
DigitalReceiver Design: Basics of Software Radio Part 4
The final article in this series on software radio coversdigital receiver applications for software radios, including a trackingreceiver system, signal intelligence receiver, direction findingsystem, radar signal processing system, and wireless cellulardevelopment system.

DigitalReceiver Design: Basicsof Software Radio: Part 3
DigitalReceiver Design: Basics of Software Radio: Part 2
DigitalReceiver Design: Basics of Software Radio:  Part 1
DSPpower-management techniques help achieve faster design cycles
Interfacingprocessors to audio and video devices
OptimizingCompilers and Embedded DSP Software
Fixed-PointDSP and Algorithm Implementation
Videoprocessing approaches for a portable multimedia SoC
DSPvideo processing via open-source APIs
Hitperformance goals with configurable processors
OptimizingPower Consumption in Embedded DSP Apps: Part 2
Howto optimize power consumption in embedded DSP applications, part 1
Interfacingprocessors to audio and video devices
Fitthe hardware to the algorithm with SystemC models
Optimizeperformance and power with dynamic power management
Howto optimize H.264 video decode on a digital baseband processor
DSPvideo processing via open-sourceAPIs
AnalyzeDSP designs in FPGAs with the z-transform
Usingmodel-based design for video processing
Unitealgorithm and hardware design flows
EncodingJPEG2000 using both DSP and FPGA
UsingEmbedded-C for high performance DSP programming
DeployingSimulink designs on your DSP
EncodingJPEG2000 using both DSP and FPGA
Harnessingparallelism from video-processing DSPs, part 2
Harnessingparallelism from video-processing DSPs, part 1
ComplexDSP system modeling made easy
Usingsimulation software to simplify DSP-based Electro-Hydraulic ServoActuator Designs: Part 3
Usingsimulation software to simplify DSP-based Electro-Hydraulic ServoActuator Designs: Part 2
Usingsimulation software to simplify DSP-based Electro-Hydraulic ServoActuator Designs: Part 3
Designingcontrol circuits for FPGA-based DSP systems
LeverageDSP-enhanced RISC cores for low-cost, power efficient, single-processorVoIP designs
Convergentprocessors solve development challenges
Videoencoding, SoC development, and TI's DSP architecture
UsingDSP technology to optimise speech recognition performance
Howto combine FPGAs and DSPs to get the best base station performance
Videoand image processing design using FPGAs
Optimizingpower consumption in embedded DSP designs
uClinuxon the Blackfin DSP Architecture: Part 3
uClinuxon the Blackfin DSP Architecture: Part 2
uClinuxon the Blackfin DSP Architecture: Part 1
PlatformFPGA design for high-performance DSPs
Usinga multicore RTOS for DSP applications
Threadversus task management in a dual mode DSP/RISC RTOS environment
DevelopingDSP code on converged hybrid DSP/RISC cores
DSPstake on next generation automotive audio processing
OptimizingDSP functions in advanced FPGA architectures
Acceleratingcomplex audio DSP algorithms with audio-enhanced DMA
MaximizingDSP, embedded CPU performance in FPGA designs

Backto the basics: Picking the right RTOS for a hybrid RISC/DSP core
Applicationdevelopment in a converged DSP/RISC environment
PlatformFPGA design for high-performance DSPs
Architectingthe right FPGA solution for your DSP design
ImplementingDSP Functions Within FPGAs
Optimizeperformance and power consumption with DSP hardware, software
Tutorial:Using high precision complex-valued arithmetic in audio DSP applications
Architectingthe right FPGA solution for your DSP design
Backto the Basics: Ensuring efficient DSP power management
Usingalgorithmic synthesis tools to simplify DSP design on FPGAs

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