More reconfigurable illogic -

More reconfigurable illogic


I always marvel at our attempts to simplify our engineering world with classic either-or debates, when reality never turns out to be that simple. Two recent articles, “The death of microprocessors,” by Nick Tredennick and Brion Shimamoto, and “Reconfigurable illogic,” by Rich Belgard, both in Embedded Systems Programming are examples of such attempts.

Tredennick and Shimamoto contend that microprocessors will be taken over by reconfigurable processors, whereas Belgard contends that too much is invested in microprocessors for significant change. While Belgard is less strident in his conclusions, noting that niche alternatives will be available, both positions partially miss what is really going on.

While they both focus on the power issue, they neglect to talk about the bigger trend: The relentless march of Moore's law is now providing more functionality on one chip than we know what to do with. It was interesting that both authors talk about ARC and Tensilica as examples of processor change or lack thereof, missing the bigger point: These companies, along with ARM and MIPs, don't sell chips, they sell IP cores. The reason: For some time now, ASIC designers have been putting entire systems on chips, not just the processors and cache, but all the other peripherals as well.

To their credit, both authors correctly allude to this. Belgard, commenting on instruction extensions to ARC and Tensilica, says “Companies creating these extensions do so to increase the performance of operations specific to these companies' specific problem domains.” Tredennick and Shimamoto say, “It's time to move the microprocessor to a supervisory role and let the application-specific logic do the work.”

In reality the architectural options form more of a continuum than an either-or proposition. ARC and Tensilica offer instruction extensions, but ARM and Sonics offer high performance buses to hook that application-specific logic into the chip along with the processor. So it really is more of a tradeoff between special instructions versus I/O communications.

In the end though, I have to side with Belgard, because the world does tend to choose solutions with the most engineering behind it. As he put it “For microprocessors, we've invested thousands of person-years in tools, . . . and we have a paradigm that works.” It turns out that the EDA industry has also invested thousands of person-years in tools and flows for ASICs.

Tredennick and Shimamoto just assume reconfigurable is the next wave because “ASICs are too expensive.” But are they? Yes, NRE costs for traditional standard cell ASICs have become increasingly expensive, but ASICs are evolving to address this issue with the recent introduction of structured ASICs, a technology that customizes, standard, coarse-grained FPGA like cell arrays with traditional ASIC-like hard-wired interconnect. These structured ASICs have a reduced number of custom masks, which keeps their NREs low.

Tredennick and Shimamoto also argue ASICs are not viable because they can't be changed, “If you customize the instruction set to optimize a camera application, that's about all the chip can be used for.”, so I have to ask why is that a problem? One structured ASIC company, eASIC, uses ebeam direct write to avoid mask costs altogether. As such, they are offering their customers zero NRE ASICs, so there is no economic disincentive there. Also Rhett Davis of Berkeley Wireless Research Center has collected benchmarks that show, as you move applications from processors to DSPs to reconfigurable hardware and on down to hardwired solutions, each step significantly improves computational performance while reducing the energy and area per calculation, of admittedly limited applications. So why wouldn't you want to optimize your camera design? Of course you would want to, and in the most targeted and efficient way possible. This goal points to hardwired ASIC solutions, and preferably for as little NRE as possible.

Tredennick and Shimamoto also miss the mark when they are concerned about power, because reconfigurable logic uses excessive amounts of power. In a paper presented at ICCAD 2002, Zuchowski found FPGAs took 67 times more silicon area and over 400 times more power than equivalent designs in standard cell1 . On the other hand, low to zero NRE structured ASICs are only half the density and use only 25 percent more power than standard cell ASICs, making them far better alternatives than reconfigurable logic, for implementing that optimized camera chip.

A structured ASIC company, eASIC, offers reconfigurable PLD like structures, on their chips, and at the same gate efficiencies as their regular logic, thus making it possible to also merge all those board level PLDs into a system level structured ASIC without having to radically alter board level system design techniques.

In conclusion, the microprocessor market is evolving towards more chip embedded and optimized chip embedded solutions, with custom logic where necessary to meet the performance power goals of the design, but as history has shown, design will not arbitrarily jump to totally new reconfigurable chips, but rather evolve toward lower cost solutions that utilize the existing ASIC infrastructure, such as structured ASICs, while utilizing the more limited reconfigurability of these structured ASICs to further evolve their architectures and design techniques. In other words, engineers almost always innovate to evolve their design activity, as opposed to revolting from what has gone before, and structured ASICs and embedded processors are prime examples of such evolution.

1 “A Hybrid ASIC and FPGA Architecture,” Paul S. Zuchowski, Christopher B. Reynolds, Richard J. Grupp,Shelly G. Davis, Brendan Cremen, Bill Troxel, Proceedings, International Conference on Computer-Aided Design , 2002.

Larry Cooke is VP of Technical Marketing for eASIC, a structured ASIC company. Previously he helped found VSIA and served as VSIA's Executive Director.

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