Motorola sees a great future for VME -

Motorola sees a great future for VME


According to research from VITA – the VMEbus International TradeAssociation, sales of VME products this year will be around$1.4billion, continuing the small but steady growth of recent years.So contrary to popular belief the 21 year old bus standard is not indecline and in fact, the Motorola Computer Group believes it is setto see increasing use for a number of reasons including thedevelopment of the faster 2eSST VMEbus standard.

In an initiative dubbed the VME Renaissance, Motorola one of thefounders of the VMEbus revolution, sees a period of innovation andperformance improvement that will help to deliver significantenhancements over the coming years, while continuing to help protectcustomers' hardware and software investments.

The VME Renaissance will begin with the launch of a PCI-X to 2eSSTVMEbus bridge codenamed 'Tempe'. The Tempe chip will implement the2eSST protocol, which has been established as a standard by VITA. Theprotocol allows the VMEbus to run at a bandwidth of 320Mbytes/s ,giving the bus an 8X performance increase over VME64's practicalspeed. Supporting existing VMEbus protocols, the chip is designed tobe backwards compatible with existing VMEbus cards, enabling existingcards and new Tempe-enabled cards to work together in the samesystem.

The Tempe chip has a PCI-X bus host-side interface running at upto 133MHz, which provides transfer rates of up to 1Gbyte/s. This is a2X improvement over a 64bit/66MHz PCI interface.

According Eric Gulliksen, an analyst from Venture DevelopersCorporation, “In 2001, the VME merchant board market in the US alonewas estimated to be $880 million. We anticipate that this newtechnology will not only ensure the continued viability of VME, butstimulate healthy growth rates for the entire VME market for the nextseveral years.”

Jeffrey Harris, director of research and software architecture,Motorola Computer Group, said, “Our complete commitment to moving theVMEbus technology forward is based on helping our current and futurecustomers compete in their respective markets. As reinforced by thesupport of key board suppliers and OEMs, it is evident that the nextfew years will be an exciting era of intense technology infusion andintellectual activity with respect to VMEbus.”

In a novel move Motorola Computer Group is looking to make theTempe chip available through a number of channels and is not rulingout enabling third parties to manufacture and supply the chip as wellas designers using it as intellectual property.

Supporting the launch of the Tempe chip is a set of bustransceivers from Texas Instruments. (TI). These transceivers, whencoupled with Motorola's Tempe chip, will allow Tempe-enabled boardsto achieve 2eSST speeds in existing VMEbus backplanes.

“Texas Instruments is looking forward to participating in the VMERenaissance with Motorola to meet the needs of the VME market,” saidDavid Hoover, worldwide marketing manager for Texas Instruments. “Weare excited about providing a product that improves signal integrityover backplanes without sacrificing high-speed . The SN74VMEH22501solution, chosen by Motorola, provides legacy VMEbus users andcurrent logic backplane designers with up to an 8X improvement inoverall system performance.”

Another major initiative in the VME Renaissance is a proposal tothe VITA Standards

Organization (VSO) to create a standard for switched serialinterconnects on the VMEbus. A number of key industry players arejoin with Motorola to form a special interest group (SIG) that willco-sponsor this proposal. The major elements in the proposalwill:

  • Add a switched serial interconnect to VMEbus coincident withthe VMEbus parallel bus;
  • Employ standard open technology for the switched seriallinks;
  • Accommodate multiple standard open technologies for the links,but not necessarily at the same time;
  • Maintain backward compatibility with the VMEbusecosystem;
  • Bring more DC power onto each VMEbus card.

The Tempe chip is expected to be available to any board developersthrough a third party reseller in the fourth quarter of 2002.

Tempe technical specifications

In addition to supporting the traditional VMEbus capabilitiesfound in today's PCI to VMEbus bridge chips, the Tempe chip alsosupports 64bit addressing and the 2eSST VMEbus protocol with transferrates to 320Mbytes/s, an 8X performance improvement over today'spractical VMEbus bandwidth of 40Mbytes/s. The Tempe chip also has aPCI-X bus interface running up to 133MHz, which provides transferrates up to 1Gbytes/s. This is a 2X improvement over a 64bit/6 MHzPCI interface. The PCI-X interface also provides other performanceenhancements over PCI such as block data transfers, splittransactions, and the elimination of wait states.

Key features of the Tempe chip include:

VMEbus Master Interface

  • Supports A16, A24, A32 and A64 address
  • Programmable VMEbus AM codes
  • Supports D8 even, D8 odd, D16, and D32 SCT transfers
  • Supports D16 BLT, D32 BLT and D64 MBLT block transfers
  • Supports SCT, BLT, MBLT, 2eVME, 2eSST protocols
  • Supports 2eSST broadcast transfers

VMEbus Slave Interface

  • Eight Programmable VMEbus map decoders
  • Supports A16, A24, A32 and A64 address
  • Supports D8 even, D8 odd, D16, and D32 single cycle datatransfers
  • Supports D8 BLT, 16 BLT, D32 BLT, and D64 MBLT blocktransfers
  • Supports SCT, BLT, MBLT, 2eVME, and 2eSST protocols
  • Supports 2eSST broadcast transfers
  • RMW cycles are not guaranteed to be indivisible on the PCIbus

PCI Bus Master Interface

  • Supports PCI-X protocol
  • Supports A32 and A64 address
  • Supports 32 and 64 data transfers
  • 4 Kbyte buffer

PCI Bus Slave Interface

  • Eight programmable PCI bus map decoders
  • Supports A32 and A64 address
  • Supports D32 and D64 data transfers
  • 8 entry command and 4 Kbyte data write post buffer
  • 4 Kbyte read ahead buffer
  • Programmable request level

Texas Instruments transceivers

The SN74VMEH22501 8-bit universal bus transceiver has two integral1bit three-wire bus transceivers and is designed for 3.3-V VCCoperation with 5V tolerant inputs. The UBTE transceiver allowstransparent, latched, and flip-flop modes of data transfer, and theseparate LVTTL input and outputs on the bus transceivers provide afeedback path for control and diagnostics monitoring. This deviceprovides a high-speed interface between cards operating at LVTTLlogic levels and VME64, VME64x, or VME320 backplane topologies.

High-speed backplane operation is a direct result of the improvedOECE circuitry and high drive that has been designed and tested intothe VME64x backplane model. The B-Port I/Os are optimised for drivinglarge capacitive loads and include pseudo-ETL input thresholds 1/2VCC±50mV for increased noise immunity. These specifications supportthe 2eVME protocols in VME64x (ANSI/VITA 1.1) and 2eSST protocols inVITA 1.5. With proper design of a 21slot VME system, a designer canachieve 320Mbyte transfer rates on linear backplanes and possibly1Gbyte transfer rates on the VME320 backplane.

All inputs and outputs are 5V tolerant and are compatible with TTLand 5V CMOS inputs.

Active bus-hold circuitry holds unused or undriven 3A-port inputsat a valid logic state. Bus-hold circuitry is not provided on 1A or2A inputs, any B-port input, or any control input. Use of pullup orpulldown resistors with the bus-hold circuitry is notrecommended.

This device is fully specified for live-insertion applicationsusing Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitryprevents damaging current to backflow through the device when it ispowered off/on.

Published in Embedded Systems (Europe) February 2002

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