Houston, Texas – Texas Instruments (TI) has announced a new multi-core DSP, the TMS320C6474. The C6474 integrates three C64x+ cores running at 1 GHz on a single die to deliver 3 GHz of DSP performance. The C6474 is TI's fastest DSP, yet it consumes 1/3 less power than single-core solutions and cuts cost and board space by a factor of three. The C6474 targets DSP farms in markets such as communications infrastructure, medical imaging, military communications and industrial vision inspection.
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The C6474 is an upgrade to the single-core C6455 DSP. Compared to this older part, the C6474 offers three times the performance for roughly the same price and footprint. The multi-core C6474 costs $261 in 100u quantities—compared to $248 for the C6455—and has a 23 x 23 mm footprint—compared to 24 x 24 mm for the C6455. The C6474 also provides a 50% improvement in power efficiency. It burns only 6.08 W, compared to 9.1 W for three discrete C6474 DSPs.
The C6474 achieves these feats partly through a process shrink from 90 nm to 65nm. The C6474 also includes TI's SmartReflex technology, which significantly reduces power. Among other things, this technology the C6474 to operate at reduced voltages when process and temperature variations allow. The C6474 is TI's first high-performance DSP to use this technology, and TI believes it has the only high-performance DSP with this capability.
The C6474 is also notable for its high levels of on-chip integration. The chip includes Viterbi and Turbo accelerators, an SGMII Ethernet MAC, Serial RapidIO (SRIO) interfaces, antenna interfaces, and a 667 MHz DDR2 memory interface. The processor also includes 3 MB of L2 memory that can be configured either as 1 MB/core or in a 1.5 MB/1 MB/0.5 MB configuration.
The C6474 greatly improves TI's positioning against the growing array of FPGAs and multicore competitors. A review of BDTI benchmark results shows that these competitors often outperform TI's single-core C6455 DSP. For example, BDTI just released results showing that Tilera's TILE64 can process OFDM channels at a cost of about $60 per channel. In comparison, the C6455 turned in a score of over $150 per channel—far worse than the TILE64. Although BDTI has not benchmarked the C6474, it is likely that this multi-core DSP will offer about the same cost per channel as the TILE64.
The C6474 is supported by the TMDXEVM6474 evaluation module (EVM), which is available for $1995. This EVM includes two C6474 processors, a high-speed DSP interconnect enabled by EMAC, AIF and SRIO SERDES interfaces, and design files such as Orcad and Gerber. The fact that the board come with two C6474 chips is a boon for DSP farm developers, as it will allow them to immediately begin working on inter-chip communications mechanisms.
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The C6474 EVM comes with a board-specific version of the Code Composer Studio (CCS) IDE. CCS already offers support for DSP farms, and the C6474 version of CCS simply brings this functionality to a multi-core processor. Thus, customers who already have DSP farm designs can easily port their designs to the C6474. However, CCS does not offer all of the features one might hope for in a multi-core IDE. For example, the IDE does not provide multi-core profiling. (The IDE can profile all cores simultaneously, but does not offer any tools specifically designed for cross-core profiling.)
For more on the C6474, see Analysis: TI's three-core, 65-nm DSP. (The C6474 is a mass-market version of the TCI6487 part discussed in that article.)
The TMX320C6474 and TMDXEVM6474 evaluation module will be available in the fourth quarter of 2008. For more information see www.ti.com/c6474pr.