Multicore is an inevitable technology, so we should get used to seeingit around. But we know that multicore already garners significantattention, especially amongst engineers deciding on which multicoreplatform to use, or trying to get up to speed on the best techniques toapply when building their applications on a multicore platform.
Applying Parallelization andLoad-Balancing
Maximizing parallelization within an application has become a key goaland challenge for multicore programmers. Programmers can obtainincreased concurrency by using multi-threading techniques.
In the session “
You will ascertain from Hillar's presentation that no matter howmuch parallelism you extract from your application, other factors suchas the processor and operating system play a key role in obtaining theultimate performance.
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These architectural differences are related to a wide variety ofdesign features such as memory interconnects, memory layout,cache-hierarchy, and CPU affinity schemes. Saladi explains theperformance variations on multicore systems in the context of barriersynchronization techniques and data sharing among threads.
Besides the architectural features associated with a specificmulticore processor, load balancing is also a key performanceconsideration to ensure proper utilization of the resources.
For the most part, it has been left to the application programmer tosolve the actual problem of how to partition, distribute, and schedulethe workload over available cores.
The session presented by Enea's Daniel Forsgren, “
Inter-Process and Inter-CoreCommunication
In addition to load balancing, another important aspect of an AMPsystem is the integration of two or more distinct operating systems.Mentor Graphics' Stephen Olsen presents “
As the complexity of operation for multiple operating systemsincreases, the use of an amalgamated inter-process communication (IPC)becomes critical. But IPC is also very applicable for other types ofinter-core communications, be it with homogeneous or heterogeneousmulticore.
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Brehmer's session also covers the application analysis and strategyfor distributing an application across multiple cores to take advantageof functional pipelining and concurrency.
As a precursor for assigning tasks to specific cores, you shouldutilize a platform-agnostic, block diagram methodology to gain moreflexibility and scalability in your application. This methodologyfurther stresses the value of the communication design, which in turnbecomes an increasingly important performance factor as the number ofcores increases in a system.
Interestingly, this can make the design task comparable to theapproach used to design hardware systems: netlists, synthesis, andsimulation. Enno Wein of ProximusDA discusses this design approach inhis session entitled “
As we've discussed, the software design aspect of inter-corecommunication has an important bearing on the performance andscalability of your system. However, the hardware aspect of theinter-core communication is equally as crucial to system performance.
High performance requirements, quality of service needs, andphysical design constraints make the integration of an increasingnumber of heterogeneous IP cores in a SoC a formidable challenge.
In the session “
Circling back to the block-level approach for software design,another one of its benefits is that it can help reduce the amount ofdependencies in a program. Although it's a more common situation withsystems based on symmetrical multiprocessing (SMP) architectures, raceconditions are one by-product of data dependencies.
You might need to significantly re-architect your application toavoid these conditions, focusing on data flow and identifying criticalcode regions. The session “
Continuing with the analysis of thread contention, Boeing's TomDickens presents “
Resolving Multicore Debug Challenges
Assuming that you have inadvertently introduced thread safety issues orany other inappropriate issues into your multicore system, finding theresultant bugs is another area that requires close scrutiny. Ericsson'sDominique Toupin points out that many problems surface only when thecomplete hardware and software components are interacting under realloads.
In Toupin's session “
Samsung Electronics' Tasneem Brutch delivers another interestingdebugging session entitled “
In the first phase, static or dynamic code analysis identifiesconcurrency-related issues including, atomicity violations, data racesand deadlocks. The output of this phase is then provided as input tothe underlying scheduler, to control the thread scheduler, and tominimize false positives which may have been identified during thefirst phase.
Visions of Virtualization
Virtualization and hypervisors are other important topics extensivelyrepresented at the Multicore Expo. Although there are manycommercially-available hypervisors, few can be used to fulfill thereal-time requirements of embedded applications.
Hypervisor integrators face many limitations in terms of the size,hardware support, guest operating system support, scalability,communication, and performance overhead. Furthermore, all solutions areproprietary, challenging system designers with complex portabilityissues if there is a need to move from one virtualization solution toanother.
Alex Bachmutsky of Nokia Siemens Networks provides an analysis ofthe majority of embedded, soft real-time and hard real-time hypervisorsand their applicability for telecommunication applications.Bachmutsky's session, entitled “
To supplement the information provided in Bachmutsky's session,Cavium Networks' Rajan Goyal covers such topics as para-virtualizationvs. full virtualization, SoC virtualization, hardware assist orco-processor virtualization.
Goyal's session, entitled “
Designing with multicore encompasses a wide variety of technologiesand techniques. The example sessions described in this articlerepresent a small portion of the material that presenters will deliverduring the Multicore Expo. These sessions will provide you with thebackground to make those critical design decisions while you areimplementing your multicore-based design.
(Markus Levy is chairman of the