In 2004 and beyond, the lines of demarcation between general-purpose processors and DSPs will continue their disappearing act. The tension between programmable and configurable solutions will tighten. But as the RISC and DSP camps maneuver to eat each other's lunch, an outrider will be making inroads. Watch for programmable logic to strengthen its foothold as a processor option.
As varied as technology choices have become for adventurous embedded designers, these trends will be driven by the immutable cost vs. performance tradeoff. The challenge for most design teams will go beyond what's best for today's design. They must weigh the cost of migrating to new solutions against the technology's future economic and performance benefits.
Designing with off-the-shelf DSPs for the past decade or so has largely been a choice between economical 16-bit fixed-point and powerful but pricy 32-bit floating point chips. That's changing quickly. The trend to more floating point options will be driven by the special needs of audio applications such as home theater and high-end car audio.
With a fixed-point processor, designers must be very careful about dynamic range and precisiontaking care not to multiply many small numbers together and then have no significant bits left; or, taking care not to multiply many big numbers and create overflows. With floating point chips, most of that design overhead goes away.
Advanced audio requires a combination of precision and dynamic range that is best served in by 32-bit floating point architectures with a 24-bit mantissa for precision and an 8-bit exponent for dynamic range. Until relatively recently, design teams on a budget had to either tweak all the performance possible out of 16-bit DSPs or use Motorola's 24-bit fixed-point 56300 architecture, which is targeted specifically for audio applications.
The other advantage of floating point architectures is the relative programming ease. Jeff Bier, president of the DSP technology consulting firm BDTI, identified the renaissance of floating point architectures in the company's recently released “Buyer's Guide to DSP Processors.”
Faster software development is a key aspect of the floating point story. Although off-the-shelf DSPs all come with impressive IP libraries, system manufacturers differentiate their products by adding their own algorithms. Concert hall acoustics is a good example. Home theater systems may have 20 or 30 algorithms, many of which are developed by the systems house. So with the rise of demanding audio applications, it looks like the trend to floating point chips will have considerable staying power.
As interesting as the off-the-shelf options are, the hottest competition in 2004 will be between solutions with strikingly different philosophies about how performance and design flexibility can co-exist. It is not news that RISC vendors have been adding more signal-processing capabilities in their processors as skyrocketing clock rates provide MIPS beyond normal control functions. It's not news that DSP companies are putting more control options on their chips in a bid to take over baseband processing.
The news is that ARM is about to launch a data engine strategy that will deliver more than an order of magnitude better signal processing performance at relatively modest clock rates. In addition, OptimoDE will generally use so few gates that they might be hard to locate on a typical ARM-based SoC.
ARM's strategy counters moves into the traditional RISC control space over the past few years by DSP leaders Texas Instruments and Analog Devices. ADI's Blackfin processor, for example, combines a 32-bit RISC instruction set, dual 16-bit multiply accumulate (MAC) DSP functionality, and 8-bit video processing performance.
TI is poised to make bigger inroads in 2004 with its dual-core OMAP architecture that ironically but quite reasonably includes an ARM 9. OMAP makes programming a dual core designs a lot easier. But TI has also gone the coprocessor route with standard parts for OEMs who don't want to design their own chips. The DM270, for example, integrates the low-power C54x DSP, the ARM7TDMI, plus video and imaging coprocessors.
Unlike the ADI and TI solutions to the signal-processing-plus-control puzzle, ARM's OptimoDE is not a dual-core solution. Granted, it is only available to SoC designersbut that includes IC companies that want to deliver off the shelf competitors to Blackfin or DM270 functionality.
Microcontroller companies, in particular, can think about delivering powerful DSP functionality where they had virtually none before. OptimoDE complements another embedded trendcompanies such as Sharp Microelectronics, Oki Semiconductor and Philips Semiconductors adopting the ARM 7 core as the engine for their 32-bit offering. It's going to be very interestingbut 2004 may be a bit early to see real products along these lines.
Because it's new, ARM's OptimoDE deserves a brief description. It's a VLIW technology with an efficient compiler paired with something that approaches graphical drag-and-drop hardware design. This hardware design is iterative. It starts with connecting library functions to create the hardware data engine. That's followed by running the algorithm's source code through the data engine simulation. Profiling tools are available to evaluate the results and identify bottlenecks. Once an optimal solution is found, the code is translated into Verilog. There's not much of a footprint on the chip. Three “heavy lifting” MPEG2 algorithmsinverse scan, DCT, and motion compensationrequire only 60K gates, according to ARM.
Where TI and ADI are pushing programmable DSPs to add flexibility to a design, ARM believes flexibility should be implemented in the data plane, says Matthew Byatt, DSP Program Manager at ARM. That's because of the 80:20 rule20% of the application's code runs for 80% of the timethrough the data engine. Meanwhile ARM, is determined to keep control plane standard with its microcontroller cores.
There's no shortage of other solutions to the performance-plus-flexibility challenge. ASIC-like solutions such as LSI Logic's RapidChip are representative of one direction. Configurable processors such as Tensilica's are another. They're all aiming for at least slightly different market segments that they have to carve out of the overall DSP market.
While the RISC and DSP camps tussle for market share in the high-end design space, in 2004 more design teams working in the 8-bit, 16-bit, and even low-end 32-bit space will realize they have powerful ways to attain design flexibility. They'll increasingly consider FPGAs with either soft or hard microcontroller cores and plenty of customizable gates as an option for reducing system cost and delivering good performance.
The leading example of this strategy is Altera's Neos soft processor core. Even designs based on a microcontroller that costs less than a dollar can be susceptible if the microcontroller does not integrate the right peripherals. FPGA solutions can win the design if:
- They are considered in the first place and
- They can deliver a lower overall system by integrating virtually all functions into a single chip.
The only designs that seem to remain off-limits to a programmable-logic solution are those that require on-chip flash or a super-low power mode or A/D conversion on chip, says Bob Garrett, Altera's Neos product manager.
Design teams can check their design against the four key advantages of FPGAs that include processor cores:
- Cost reduction in terms of system level integration
- Design reuse in cases where 10 designs are really just variations on one
- Creating an exact fit for a microcontroller/peripherals combination
- Future proofing the design against discontinued microcontroller variants.
Soft-core-based FPGA designs also have the ride on the performance boost of each new FPGA design node. The chips run at higher clock rates but the IP doesn't change at all. Many design teams have already caught the wave.
Gartner Dataquest has forecast that FPGAs with embedded processors will account for one-third of all FPGA design starts by the end of the decade and that soft core processors will capture 75% of them, according to Altera's Garrett. Altera has sold 12,000 Neos design kits in the past three years and a 2002 survey conducted by Embedded Systems magazine surprisingly found Neos in the top 10 of “processors being considered for the next design” by embedded designers. It was close to the bottom of the top 10 but that's not bad for a three-year old soft core.
The competition between RISC and DSP hardware vendors will complicate life for development tools vendors and users alike. Dual core systems, in particular, need a means of communicating between the RISC and DSP processors. Data engines can require instruction set extensions and DSP functionally such support for circular buffers, hardware loops, and accumulators.
Because of the complexity of dual-core systems, 2004 may see an uptake in DSP operating system adoption. Most DSP customers are still questioning the value of an RTOS but some are starting to see a benefit as they enter the dual-core environment, according to Nikolas Gustasson, DSP marketing manager at Enea Embedded Systems.
Meanwhile, the popularity of DSP-based solutions will fuel a growth trend in the market for DSP development tools. Green Hills Software leads the way here, according to Marketing Vice President Craig Franklin, but as a third-party tools developer for DSP companies.
On the business side of embedded software, Linux has made some inroads largely through the efforts of MontaVista Software. Using Linux for management functions and a DSP OS for everything else is one way to get around Linux's drawbacks. But the underlying Linux trend may actually be its royalty free business model.
No assessment of trends in embedded systems for 2004 would be complete without at least a quick look at the military marketsince it can easily translate into the homeland security market in the U.S.
The U.S. military is especially interested in reconfiguring communication hardware on the fly. The primary program espousing this goal is the Joint Tactical Radio System (JTRS). A typical scenario would involve deploying forces to a new theater and installing a new, highly secure communication system that a multinational team can use.
New encryption and modulation schemes would be deployed over the air very quickly with the option of changing them again in the next hour, day, or week, says Rodger Hosking, vice president of Pentek, a high-end board supplier to the military and government.
FPGAs are the logical technology to implement this system that allows foot soldiers, tanks, drone aircraft, satellites, and a command center communicate over a battlefield Internet-like mesh that assures redundancy and fault tolerance. This essentially allows everyone to operate with the same battle plan.
So there you have it. A bewildering collection of cross-over and hybrid technologies will be available to designers in 2004: standard parts that bundle the functionally once reserved for ASICs; a raft of solutions that provide the flexibility to implement signal processing algorithms, and FPGA technology likely to find its way into many applications as more than just programmable gates.