The ModelSim Xilinx Edition II (MXE II) tool version 5.6a supports new hierarchical netlist capabilities and is available exclusively through Xilinx. Improvement have also been made to productivity in the ModelSim simulation environment.
The exclusive hierarchical netlist feature allows engineers to shorten their design cycle by simplifying the time consuming process of correlating timing simulation results with the original RTL source code during design debug. ModelSim and Xilinx hierarchical netlist generation also work in concert with Xilinx exclusive incremental design, enabling verification engineers to focus their efforts only on areas of a design that have changed.
Preserving the placement and routing of unchanged portions also guarantees the performance of those blocks. This means customers using an incremental design flow can focus their design debug efforts on areas of the design that have changed as a result of design revisions.
“Improving the debug cycle time is a constant driver for product development at Model Technology,” said John Lenyo, director of marketing of Model Technology, a subsidiary of Mentor Graphics.
“Combining Xilinx's incremental design and hierarchical netlist features with ModelSims industry-leading simulation debug capabilities will enable designers to significantly reduce the time it takes to find and fix problems.”
MXE II enhances designer productivity by including a variety of new features that accelerate design verification. Built in language templates enable users to create VHDL or Verilog quickly with only a few mouse clicks while testbench wizards, allow users to create common testbench functions with easy to use wizards.
Simulation configurations support the creation and storage of simulation environment attributes in a file that can be reused during future design simulations and an automatic compilation, automating the recompilation sequence required for subsequent simulations.
ModelSim XE II is available under an annual license which includes maintenance and is also available in a bundled configuration that includes design entry, synthesis, simulation and implementation tools.
Published in Embedded Systems (Europe) November 2002