Network on chip eases IP connect - Embedded.com

Network on chip eases IP connect

PARIS, France — Arteris has developed a complete solution for creating Networks-on-Chip (NoC) which is used to connect and manage the communication between the variety of design elements and intellectual property blocks required in complex system-on-chips. The company's proprietary IP library uses a packet-based switch fabric in conjunction with its NoC specific design tools to generate unique NoC instances.

The result is said to overcome the limitations of traditional bus-based methods, while maintaining compatibility with existing interface standards and design tool flows. While NoC has been an emerging area of academic and research interest, Arteris believes it is the first to provide a commercial solution for chip designers.

Like the networking of computers, NoC provides an efficient means to manage communications among any collection of distributed systems, which in the case of a complex SoC can be individual IP blocks and/or clusters of functionality that all must communicate with each other.

The proliferation of tens, even hundreds, of IP blocks on a single chip, as well as the advent of ultra-thin line widths in deep submicron processes, have made traditional on-chip communications methods such as buses an increasingly substantial obstacle in the way of realizing the full potential of SoC implementations.

To enable improved system performance, achieve critical timing requirements, and facilitate more efficient IP use (and re-use), Arteris' solution borrows applicable networking techniques and implements them in its NoC Solution.

The solution uses fundamental networking units, such as switches and links, in the form of configurable IP blocks, combined with design exploration and compilation tools that generate the completed NoC for common design tool flows, in the form of high-level description formats such as SystemC and synthesizable Verilog or VHDL.

Arteris' proprietary packet-based NoC Transaction and Transport Protocol (NTTP) ensures compatibility with all major on-chip SRAM blocks and socket standards (AMBA AHB, AMBA AXI, OCP 2.0), and also supports key off chip interfaces such as Denali's Databahn DDR memory controller IP.

A point-to-point physical implementation leverages the Globally Asynchronous Locally Synchronous (GALS) paradigm, with demonstrated operating frequencies of 750MHz or more in 90nm silicon process, using standard cells libraries and off-the-shelf EDA tools.

The Arteris NoC Solution consists of the Danube Intellectual Property Library that contains a set of configurable building blocks managing all on-chip communications between IP cores in SoC designs, and a suite of design tools for configuring and implementing the IP library as synthesizable RTL.

The Danube IP library is comprised of three types of units: Network Interface Units providing interfaces to the IP cores, Packet Transport Units and physical links building up the switch fabric user-defined topology.

These units can be configured based on the system objectives and topology requirements. The building blocks implemented in Danube IP use a GALS method to span distance and cross clock boundaries on the chip. An on-chip protocol 'spy' is provided for runtime system-level debug.

Arteris' NoCexplorer exploration tool provides an intuitive environment to capture the dataflow requirements of the IP blocks to be serviced by the NoC and allows the designer to analyze various NoC topologies to achieve optimal performance and area implementation.

NoCexplorer tool Click here for larger version

The NoCcompiler' design tool creates a database of the specific instance of the NoC. It generates a variety of views of the NoC, in Verilog, VHDL, SystemC, or other standard formats.

Its outputs are compatible with standard ASIC design flows, including a SystemC cycle-accurate model, synthesizable RTL descriptions, FPGA-optimized output for prototyping, and synthesis scripts.

See this story in the April 2005 issue of Embedded Systems Europe

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