New AI/ML processor supports SoCs and chiplets for smart edge devices - Embedded.com

New AI/ML processor supports SoCs and chiplets for smart edge devices

CEVA’s latest NeuPro-M supports both system-on-chip and heterogeneous SoC scalability, targeting edge AI/ML and edge compute.

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CEVA, Inc. has launched its latest generation processor architecture for artificial intelligence and machine learning (AI/ML) inference workloads. The new NeuPro-M is a self-contained heterogeneous architecture composed of multiple specialized co-processors and configurable hardware accelerators that seamlessly and simultaneously process diverse workloads of deep neural networks, boosting performance by 5-15X compared to its predecessor.

The new architecture supports both system-on-chip (SoC) as well as heterogeneous SoC (HSoC) scalability to achieve up to 1,200 TOPS and offers optional robust secure boot and end-to-end data privacy. NeuPro–M compliant processors initially include the following pre-configured cores:

  • NPM11 – single NeuPro-M engine, up to 20 TOPS at 1.25GHz
  • NPM18 – eight NeuPro-M engines, up to 160 TOPS at 1.25GHz

As an example of its performance, a single NPM11 core, when processing a ResNet50 convolutional neural network, achieves a 5X performance increase and 6X memory bandwidth reduction versus its predecessor, which results in power efficiency of up to 24 TOPS per watt.

NeuPro-M is capable of processing all known neural network architectures, as well as integrated native support for next-generation networks like transformers, 3D convolution, self-attention and all types of recurrent neural networks. NeuPro-M has been optimized to process more than 250 neural networks, more than 450 AI kernels and more than 50 algorithms. The embedded vector processing unit (VPU) ensures future proof software-based support of new neural network topologies and new advances in AI workloads. In addition, the CDNN offline compression tool can increase the FPS/Watt of the NeuPro-M by a factor of 5-10X for common benchmarks, with very minimal impact on accuracy.

Ran Snir, vice president and general manager of the vision business unit at CEVA, commented, “The artificial intelligence and machine learning processing requirements of edge AI and edge compute are growing at an incredible rate, as more and more data is generated and sensor-related software workloads continue to migrate to neural networks for better performance and efficiencies. With the power budget remaining the same for these devices, we need to find new and innovative methods of utilizing AI at the edge in these increasingly sophisticated systems.”

He continued, “NeuPro-M is designed on the back of our extensive experience deploying AI processors and accelerators in millions of devices, from drones to security cameras, smartphones and automotive systems. Its innovative, distributed architecture and shared memory system controllers reduces bandwidth and latency to an absolute minimum and provides superb overall utilization and power efficiency. With the ability to connect multiple NeuPro-M compliant cores in a SoC or chiplet to address the most demanding AI workloads, our customers can take their smart edge processor designs to the next level.”

The NeuPro-M heterogenic architecture is composed of function-specific co-processors and load balancing mechanisms that are the main contributors to the huge leap in performance and efficiency compared to its predecessor. By distributing control functions to local controllers and implementing local memory resources in a hierarchical manner, the NeuPro-M achieves data flow flexibility that result in more than 90% utilization and protects against data starvation of the different co-processors and accelerators at any given time. The optimal load balancing is obtained by practicing various data flow schemes that are adopted to the specific network, the desired bandwidth, the available memory and the target performance, by the CDNN framework.

Ceva NeuPro-M_Architecture_Block_Diagram
The NeuPro-M block diagram. (Image: CEVA)

The architecture highlights include:

  • Main grid array consisting of 4K MACs (multiply and accumulates), with mixed precision of 2-16 bits.
  • Winograd transform engine for weights and activations, reducing convolution time by 2X and allowing 8-bit convolution processing with <0.5% precision degradation.
  • Sparsity engine to avoid operations with zero-value weights or activations per layer, for up to 4X performance gain, while reducing memory bandwidth and power consumption.
  • Fully programmable vector processing unit, for handling new unsupported neural network architectures with all data types, from 32-bit floating point down to 2-bit binary neural networks (BNN).
  • Configurable weight and data compression down to 2-bits while storing to memory, and real-time decompression upon reading, for reduced memory bandwidth.
  • Dynamically configured two level memory architecture to minimize power consumption attributed to data transfers to and from an external SDRAM.

To illustrate the benefit of these features, concurrent use of the orthogonal mechanisms of Winograd transform, Sparsity engine, and low-resolution 4×4-bit activations, delivers more than a 3X reduction in cycle count of networks such as Resnet50 and Yolo V3.

As neural network weights and biases and the data set and network topology become key intellectual property of the owner, there is a strong need to protect these from unauthorized use. The NeuPro-M architecture supports secure access in the form of optional root of trust, authentication, and cryptographic accelerators.

For the automotive market, NeuPro-M cores and its CEVA deep neural network (CDNN) deep learning compiler and software toolkit comply with automotive ISO26262 ASIL-B functional safety standard and meets the stringent quality assurance standards IATF16949 and A-Spice.

Together with CEVA’s neural network compiler and its robust software development environment, NeuPro-M provides a fully programmable hardware/software AI development environment for customers to maximize their AI performance. CDNN includes software that can fully utilize the customers’ NeuPro-M customized hardware to optimize power, performance & bandwidth.

The CDNN software also includes a memory manager for memory reduction and optimal load balancing algorithms, and wide support of various network formats including ONNX, Caffe, TensorFlow, TensorFlow Lite, Pytorch and more. CDNN is compatible with common open-source frameworks, including Glow, tvm, Halide and TensorFlow and includes model optimization features like ‘layer fusion’ and ‘post training quantization’ all while using precision conservation methods.


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