New Atmel XMEGA A3B sub-100nA MCU guarantees 62.5 nS response time - Embedded.com

New Atmel XMEGA A3B sub-100nA MCU guarantees 62.5 nS response time

Boston, Ma. – At the Embedded Systems Conference here, Atmel took the wraps off its low power, 32 MIPS 8-bit XMEGA A3B microcontroller.

It incorporates an 8-channel event system and 4-channel DMA controller that allow up to eight inter-peripheral signals and up to four 8 Mbps data transfers to occur simultaneously, while the CPU is in idle sleep mode.

According to Kristian Saether, AVR Product Marketing Manager, no context switching or interrupt latency is required and the XMEGA, drawsjust 10 mA (at 32 MHz) to execute all these tasks. According to the company, a conventional single-cycle RISC MCU would require 64 MIPS and consume 32 mA executing the same tasks, due to extensive context switching and interrupt latency.

XMEGA event response time is as fast as 31.2 nS ” 80 times faster than a conventional 8-bit MCU and 20 times faster than a 32-bit MCU. A 65.2 nS response time is guaranteed.

Event system guarantees 62.5 nS response time, conserves power. The XMEGA A3B allows autonomous and instantaneous peripheral-to-peripheral interaction to be triggered by timer/counter compare match or overflow, analog comparator toggle, pin change, ADC complete or compare, and real time counter overflow.

Saether said these events can trigger actions in other peripherals that include ADC or DAC conversion, input capture to time stamp communication or the ADC measurements, external frequency or pulse-width measurements, clocking of timer/counters, starting a DMA transaction, or changing a pin output.

The triggering of events and resulting actions on the XMEGA are fully configurable in software and can be kept static and locked, or can change dynamically during various stages of the application execution.

“There is no software overhead and critical tasks are handled with a guaranteed latency of 2 cycles (62.5 nanoseconds at 32 MHz) and without CPU overhead,” he said. “For example, a pin-change on any I/O pin or overflow on any timer/counter can trigger ADC conversions, with the result transferred over a DMA channel to the SRAM.

At the same time, a second timer/counter can trigger high speed DAC conversion that uses a second DMA channel for data. The event system can make the analog comparator trigger input capture for 100% accurate time stamps, automatic capture to time stamp the beginning of communication transactions, or ADC conversion scans.”

The remaining four event channels and two DMA channels are available for fault protection of a PWM output controlling a high voltage driver stage, cascading of timer/counters, and a couple of communication channels and ” all at the same time, all while the CPU is sleeping.

Depending on packaging, pinout, the amount of on-board Flash (64 TO 256 Kbits), and SRAM (4 to 8 Kbits), the XMEGA A3B MCUs range in price from $3.12 to $4.59 each in 10,000 unit quantities. To learn more, go to www.atmel.com.

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