Fabless semiconductor startup Astera Labs has announced a new purpose-built CXL 2.0 and PCIe 5.0 connectivity solutions to unlock heterogeneous compute architectures and address latency sensitive workloads in the data center. The company said the aim of these new solutions is to address system-wide performance bottlenecks in data-centric applications.
The proliferation of data and mainstreaming of specialized workloads – like artificial intelligence (AI) and machine learning (ML) – require purpose-built accelerators to work side-by-side with general-purpose CPUs on the same motherboard or within the same rack while sharing a common memory space. CXL 2.0 interconnect is key to enable such cache coherent system topologies.
The first product in Astera Labs new portfolio is its Aries Compute Express Link (CXL 2.0) smart retimer portfolio (PT5161LX, PT5081LX) for low-latency CXL.io connectivity, which is actively being sampled to strategic customers. The company’s CEO, Jitendra Mohan, said, “With our expansion into the CXL ecosystem, Astera Labs is taking another giant leap to provide purpose-built solutions that unlock complex heterogeneous compute and composable disaggregation system topologies.”
The CXL 2.0 specification was released by the CXL Consortium in November 2020. CXL is an open industry-standard interconnect offering coherency and memory semantics using high-bandwidth, low-latency connectivity between host processor and devices such as accelerators, memory buffers, and smart I/O devices. The CXL 2.0 specification adds support for switching for fan-out to connect to more devices; memory pooling for increased memory utilization efficiency and providing memory capacity on demand; and support for persistent memory. All of this is while preserving industry investments by supporting full backwards compatibility with CXL 1.1 and 1.0.
The president of the CXL Consortium, Barry McAuliffe said, “As an early CXL Consortium member, Astera Labs contributed its connectivity expertise to the advancement of the CXL standard. It is great to see its first CXL silicon implementation come to market in support of a fast-growing CXL ecosystem.”
New PCIe 5.0 solutions in collaboration with Intel
Astera Labs also announced availability of a new low latency mode in its Aries smart retimer portfolio for PCIe connectivity with Intel Xeon scalable processors. This development was the result of close collaboration with Intel Corporation to further reduce latency in PCIe links to sub-10ns and enhance performance in data-centric workloads. Astera Labs claimed it is the first vendor to demonstrate robust PCIe 5.0 interoperability with Intel Xeon Scalable processors code-named ‘Sapphire Rapids.’
Also launched at the same time is a new plug-and-play Smart retimer add-in-card for PCIe/CXL applications, called Equinox. Also developed in partnership with Intel, the card and associated purpose-built firmware will simplify development of PCIe 5.0 enabled systems with Intel’s latest Xeon Scalable processors. This represents Astera Labs’ transition to offer easy-to-use, plug-and-play boards to rapidly implement complex system topologies.
“PCIe Gen5 and CXL are foundational technologies to heterogeneous compute workloads and data center architectures today and tomorrow,” said Zane Ball, corporate VP and general manager for datacenter engineering and architecture at Intel. “Intel is collaborating with ecosystem leaders like Astera Labs to significantly reduce PCIe and CXL interconnect latency on upcoming Intel Xeon Scalable platform code-named ‘Sapphire Rapids’ and additional platforms.”
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