New EDA Design Tool Addresses Heterogenous Systems Integration - Embedded.com

New EDA Design Tool Addresses Heterogenous Systems Integration

A new EDA design tool claims to be the first commercially available platform enabling fully integrated, design environment-agnostic IC and packaging co-design of 2D/2.5D/3D heterogenous systems.

The GENIO tool from Monozukuri Technologies, a startup from Rome, Italy, integrates existing silicon and package EDA flows to create full co-design and I/O optimization of complex multi-chip designs that comprise advanced heterogeneous microelectronic systems.  The company said it is the first tool to seamlessly work across all existing EDA flows to maximize design efficiency and system optimization.

Founder and CEO Monozukuri, Anna Fontanelli, said, “GENIO is not a promise or partial solution.  It a breakthrough, ground-up tool that is ready for implementation today. She said its holistic design environment includes complete floor planning, I/O planning and end-to-end interconnect planning combined with cross-hierarchical pathfinding optimization. The emphasis is on being agnostic to all EDA flows, which means it is not a ‘bolt on’ capability like other co-design options. It is a total re-conceptualization and implementation that maximizes design efficiency across system level design.

The cross-hierarchical, 3D-aware, design methodologies streamline the entire IC ecosystem, integrating IC and advanced packaging design to ensure full system level optimization, shortening the design cycle, driving faster time-to-manufacturing and improving yields.

The tool’s Duet graphic user interface (GUI) creates an environment where cross-fabric structures can be imported, created, and stored in a common database. The system’s efficient automation allows designers to create, explore, optimize and compare different floor-planning, scenarios and dynamically modify and store optimization results according to the final configuration.

As an integrated IC and packaging co-design EDA tool, Monozukuri said GENIO sets a new benchmark for creating heterogeneous microelectronic systems-level design for advanced applications such as artificial intelligence, virtual reality and web scale infrastructure.

Monozukuri was incorporated in Rome in 2014 and developed its technology under the Horizon 2020 European project to develop a heterogeneous integrated platform for electronic system redistribution, or HIPER.  This project aimed to redefine the co-design of heterogeneous microelectronic systems by providing an improved level of automation in three-dimensional interconnect optimization. Its premise was that as electronic systems become more heterogeneous and complex, this creates a real problem for developers needing to carefully plan the interfaces between these components. This can add significant time in the development process and result in a sub-optimal design with increased wire crossings, wire length and cost. It also increases the chance of an error being made in design which can lead to significant costs in terms of either re-design.

Heterogeneous integration is the way industry is moving to overcome the limitations of Moore’s Law in enhancing performance. But the diverse nature of silicon and package technologies and the use of high-speed interconnections calls for enhancements in co-design capabilities to enable planning, implementation and analysis across different engineering domains as well as to provide a complete, consistent model across tool platforms.

Monozukuri said this is where its GENIO tool comes in, as an add-on to cover the missing piece of the EDA puzzle needed to complete these next generation system designs. Enabling I/O resource planning and optimization, it helps address the communication among the compute, memory, interface, sense and actuate components of the final system.

TSV-management Monozukuri
The co-design tool helps identify the best stack configuration by enabling vertical shuffling of multiple ICs across the 3D Stack, supporting the ability to minimize the overall number of TSVs (through-silicon vias) needed and optimize the system interconnect. (Image: Monozukuri)

The design tool provides chiplets/die, silicon interposer, package, and surrounding PCB co-design features that are key to achieve the area, power, and performance targets, without being overwhelmed by the complexity of the system interconnect. To enable planning, implementation and analysis across different engineering domains as well as to provide a complete, consistent model across tool platforms the GENIO product family adds key co-design features such as:

  • an integrated environment providing the system model across the platforms used for implementation and analysis of digital die, analog die, package, and PCB portions, with bidirectional data representation between GENIO and each platform.
  • a single, consistent interconnect manager able to represent and maintain the interconnect model of the entire system – connectivity between silicon die micro-bumps, interposer routes/vias, through-silicon vias, and package bumps – replacing the error prone process of spreadsheet exchange between engineering team
  • a unique cross-hierarchical 3D-aware pathfinding engine able to identify the best interconnect in a 3D space, driven by physical and electrical design constraints. this automates the optimization of up to hundreds of thousands of connections while reducing the number of physical resources needed for implementation.

 

 

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