New FPGA family cuts power consumption - Embedded.com

New FPGA family cuts power consumption

CrossLink-NX FPGAs are built on the Lattice Nexus platform, which combines a 28-nm fully depleted silicon-on-insulator (FD-SOI) manufacturing process with a fabric architecture optimized for low power in a small form factor.
Aimed at embedded vision and edge AI designs, CrossLink-NX FPGAs provide up to 75% lower power consumption than similar-class competitive FPGAs.

The first device in the CrossLink-NX series is offered in a 6 x 6-mm package, up to 10 times smaller than similar FPGAs, and is well-suited for outdoor, industrial, and automotive applications. CrossLink-NX FPGAs achieve a soft error rate (SER) that is up to 100 times lower than comparable devices, enabling their use in mission-critical applications.

The series furnishes multiple high-speed I/Os, including MIPI, PCIe, and DDR3 memory, and a high memory-to-logic ratio featuring 170 bits of memory for every logic cell. Fast configuration — I/O in 3 ms and total device in less than 15 m — affords instant-on performance for applications where long system boot time is unacceptable.

CrossLink-NX FPGAs are supported by a robust library of design software, IP blocks, and application reference designs. Originally scheduled for availability in 2020, Lattice is releasing CrossLink-NX ahead of schedule and is already sampling devices to select customers.

>> This article was originally published on our sister site, EDN.

 

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