In the first major revision of the specification in twelve years, the IEEE has just released the new 1149.1-2013 Standard for Test Access Port and Boundary-Scan Architecture.
Commonly known in the industry as JTAG for “Joint Test Action Group” the new standard is aimed at lowering electronics industry costs by enabling test re-use across all phases of the integrated circuit (IC) lifecycle via vendor-independent, hierarchical test languages.
According C.J. Clark, chair of the IEEE 1149.1 working group and chief executive officer of Intellitech, this is the first revision for the standard since 2001.
“It allows critical domain expertise for intellectual property (IP), such as how to configure a serializer/deserializer (SERDES) for loopback testing, for example to be transferred in a computer-readable format from the IP designer to IC designers,” he said.
“They, in turn, can transfer it designers of printed circuit boards (PCBs) and to test engineers, gradually magnifying industry cost savings along the supply chain. The cost savings for the electronics industry that IEEE 1149.1-2013 is intended to unlock are estimated to be in the billions of dollars.”
IEEE 1149.1-2013 specifies a new hierarchical Procedural Definition Language (PDL)—a standard test language based on TCL, and hierarchical extensions to the original Boundary Scan Description Language (BSDL) to describe on-chip IP test data registers.
Eight new optional IC instructions provide a foundation for configuring I/Os for board test, mitigating false failures when re-testing the IC at the board level and correlating the results back to wafer level test through an Electronic Chip ID.
Clark believes the revision will have a major impact on how business is done across the electronics industry, from IP providers to silicon vendors to system integrators, because it was defined to eliminate inefficient engineering.
“The IP provider can document the IP test interface and how to operate the IP in an English-like language—just once, for all ICs,” he said. “Software tools then re-target this documentation at the IC and board level for tests.
In revising IEEE 1149.1, said Clark, the working group focused on two things: lowering industry costs through the new PDL language and enabling test re-use over the lifecycle of an integrated circuit.
“Now, for the first time in our industry, a standard overcomes the 'Tower of Babel' language differences,” he said, “and enables on-chip tests to be re-used and correlated across IC, board and field automatic test equipment (ATE).”
He said the working group also spent a lot of effort incorporating features that were synergistic with two other industry standards. For one thing, it supports segmented on-chip test data registers that cross power domains specified by IEEE 1801™-2013 “Standard for Design and Verification of Low Power Integrated Circuits”.
The new JTAG standard also enables descriptions and operation of IP accessible via the IEEE 1500-2005 “Standard Testability Method for Embedded Core-based Integrated Circuits” structures.” He said IEEE 1500 is frequently used for production IC testing and JTAG 2013’s domain segmentation adds new capability to the IEEE 1500 Wrapper Serial Ports.
The new features of IEEE 1149.1-2013 also address the problems of describing and managing chips with complex programmable I/Os or chips with multiple power domains.
“Private instructions and test data registers can be documented and tool support for them can be automated,” said Carol Pyron, vice chair of the IEEE 1149.1 working group and senior member of technical staff with Freescale Semiconductor.
IEEE 1149.1-2013 is available for purchase at the IEEE Standards Store.