New ML-based tool offers automated chip design flow optimization -

New ML-based tool offers automated chip design flow optimization

Cadence Design Systems has introduced a new tool that uses machine learning (ML) to drive the Cadence RTL-to-signoff implementation flow, delivering what it said is up to 10X productivity and 20% PPA improvements.

There’s no debating the fact that chip design is getting more and more complex as customers demand more features and smaller devices and lower power consumption. To meet this demand, engineers are becoming overloaded and need support to keep up with demand and timely product development.

To address this, Cadence Design Systems has introduced a new tool that uses machine learning (ML) to drive the Cadence RTL-to-signoff implementation flow, delivering what it said is up to 10X productivity and 20% PPA (power, performance and area) improvements for implementation. Its new Cerebrus Intelligent Chip Explorer provides more efficient on-site and cloud compute resource management capabilities than traditional human-driven design exploration; and improves PPA and productivity across many nodes and multiple end-applications including consumer, hyperscale computing, 5G communications, automotive and mobile design.

In a briefing with, Rod Metcalfe, a product management group director at Cadence, said, “This is the first full flow digital optimization tool using ML. This is important, as design complexity grows, chip design demands more features and intelligence, yet there is a constraint on the number of engineers available to carry out these tasks. We still see designers doing manual flow development and iterate around the loop to meet their design goals: this requires a huge amount of engineering effort and is not scalable. That’s where Cerebrus comes in, using massive compute to improve productivity for design automation.”

Metcalfe highlighted an example where Cerebrus needed just one engineer to converge on an improved design flow within 10 days to automatically improve the PPA of a 5nm mobile CPU (see graphic below).

Cadence Cerebrus productivity example
Using the ML-based tool provides better PPA and full flow productivity. (Source: Cadence)

Another example at a higher level is automated floorplan optimization, as in the graphic below:

Cadence Cerebrus floorplan example
The Cerebrus tool also provides automated floorplan optimization. (Source: Cadence)

The impact of using an ML-based tool like Cerebrus is that design teams have an automated way to reuse historical design knowledge – previously they would have spent excess time on manual re-learning with each new project. Hence Cadence said Cerebrus marks an EDA industry revolution with ML-driven digital chip design where engineering teams have a greater opportunity to provide higher impact in their organizations because they can offload manual processes. As the industry continues to move to advanced nodes and design size and complexity increase, Cerebrus will help designers achieve PPA goals more efficiently.

Early customer endorsements for the tool came from Renesas and Samsung Foundry.

Satoshi Shibatani, director of the digital design technology department in the shared R&D EDA division of Renesas, said, “To efficiently maximize the performance of new products that use emerging process nodes, digital implementation flows used by our engineering team need to be continuously updated. Automated design flow optimization is critical for realizing product development at a much higher throughput. Cerebrus, with its innovative ML capabilities, and the Cadence RTL-to-signoff tools have provided automated flow optimization and floorplan exploration, improving design performance by more than 10%.”

Meanwhile at Samsung Foundry, its vice president for design technology, Sangyun Kim, said, “As we continue to deploy up-to-date process nodes, the efficiency of our design technology co-optimization (DTCO) program is very important. . As part of our long-term partnership with Cadence, Samsung Foundry has used Cerebrus and the Cadence digital implementation flow on multiple applications. We’ve observed more than an 8% power reduction on some of our most critical blocks in just a few days versus many months of manual effort. In addition, we are using Cerebrus for automated floorplan power distribution network sizing, which has resulted in more than 50% better final design timing.

Key features and benefits of Cerebrus are:

  • Reinforcement ML: quickly finds flow solutions human engineers might not naturally try or explore, improving PPA and productivity.
  • ML model reuse: allows design learnings to be automatically applied to future designs, reducing the time to better results.
  • Improved productivity: lets a single engineer optimize the complete RTL-to-GDS flow automatically for many blocks concurrently, allowing full design teams to be more productive.
  • Massively distributed computing: provides scalable on-premises or cloud-based design exploration for faster flow optimization.
  • Easy-to-use interface: powerful user cockpit allows interactive results analytics and run management to gain valuable insights into design metrics.

Cerebrus is part of the broader Cadence digital full flow, working seamlessly with the Genus synthesis solution, Innovus implementation system, Tempus timing signoff solution, Joules RTL power solution, Voltus IC power integrity solution, and Pegasus verification system to provide customers with a fast path to design closure and better predictability.

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