New Renesas ASSPs based on Andes RISC-V to sample in 2021 - Embedded.com

New Renesas ASSPs based on Andes RISC-V to sample in 2021

As part of a technology intellectual property (IP) cooperation, Renesas Electronics Corporation has announced it will embed Andes Technology’s AndesCore™ IP 32-bit RISC-V CPU cores into its new application-specific standard products that will begin customer sampling in the second half of 2021.

The delivery of Renesas’ pre-programmed ASSP devices based on the RISC-V core architecture, combined with specialized user interface tools to set the application programmable parameters, will provide customers with complete and optimized solutions. According to Renesas, this capability eliminates the initial RISC-V development and software investment barrier. In addition, a network of regional Renesas partners with specialized expertise will provide focused customer support.

The President of Andes Technology Corp, Frankwell Lin, said, “We are thrilled that Renesas, a top-tier global MCU provider has designed Andes RISC-V cores into their pre-programmed application-specific standard products. Renesas and Andes share the same vision to welcome the era of RISC-V being the mainstream CPU instruction set architecture (ISA) for system-on-chips (SoC). Not only does this represent a milestone for Andes, but it marks the arrival of the open-source RISC-V ISA as a mainstream computing engine. Renesas customers will benefit from a modern ISA constructed for the needs of 21st century computing.”

Speaking for Renesas, Sailesh Chittipeddi, executive vice president and general manager of its IoT and infrastructure business unit, commented, “The scalable range of performance, selectable safety features, and customization options provided by the Andes RISC-V core IP enables Renesas to provide innovative solutions for future application-specific standard products.  Customers looking for cost-effective alternative paths for existing or emerging applications will benefit from the reduced time to market and lower development costs.”

The RISC-V offer from Andes has been gaining some traction.

For example, Picocom, a semiconductor startup that designs and markets open RAN (radio access network) standard-compliant baseband SoCs and carrier-grade software products for 5G small cell infrastructure, recently said it selected the AndesCore N25F RISC-V 32-bit core integrated with the AE350 peripherals platform for its forthcoming 5G small cell distributed unit (DU) SoC. Picocom is championing ‘open RAN’ – the disaggregation of 5G radio access networks (RAN), which will open up the supply chain enabling new vendors to enter the market and compete. With Andes’ performance efficient cores, Picocom’s DU baseband offload SoC will deliver the needed flexibility, efficiency and performance to meet the challenges brought by 5G small cells, according to Picocom.

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