New tool tackles layout vs schematic verification of early “dirty” designs - Embedded.com

New tool tackles layout vs schematic verification of early “dirty” designs

Increasing chip design complexity and size means tapeouts are getting harder and taking longer due to the corresponding escalation in the number of verification operations. To address one aspect of this process, Mentor, a Siemens busines, has introduced a tool to help circuit verification teams rapidly examine “dirty”, immature and early stage designs to analytically discover specific types of layout vs schematic (LVS) violations and fix them earlier and faster.

Its new Calibre nmLVS-Recon solution helps speed overall circuit verification turnaround time by enabling system-on-chip (SoC) engineers, circuit designers, and IC circuit verification teams to identify and resolve selected systemic errors early in the development phase. These types of violations can consume valuable compute resources and potentially generate millions of error results, many of which are due solely to the incomplete status of the design. Mentor said early adopter customers leveraging Calibre nmLVS-Recon realized more than 10x runtime improvements and 3x less memory requirements when analyzing early-stage designs.

The tool is an extension of Mentor’s Calibre suite of early verification technologies designed to enable customers to automatically and accurately analyze IC designs for errors during early-stage verification design iterations. The first implementation introduced in 2019 was the Calibre nmDRC-Recon solution for physical verification teams to scan early-stage designs to methodically find and fix selected classes of design rule checking (DRC) errors earlier and faster, before running full-chip signoff DRC.

The Calibre nmLVS-Recon solution provides a similar benefit by delivering an intelligent process providing options for data partitioning, data re-use, task distribution, and errors management to help achieve faster layout vs. schematic iterations on dirty designs. Designs containing gross systemic violations (such as shorted nets) not only generate thousands of error results, but also degrade the runtime and scalability of a full LVS iteration by requiring extensive hardware resources. Hence verification engineers can use the Calibre nmLVS-Recon process to interactively and iteratively find and fix these types of violations quickly and efficiently, until the design is ready for full-chip signoff LVS iterations.

The Calibre nmLVSRecon process targets selected circuit verification requirements to enable greater efficiency by solving the highest priority issues in layout vs schematic verification (Image: Mentor)

The Calibre nmLVS-Recon technology is based on a flexible configuration framework that enables multiple use models, allowing design teams to select and analyze specific classes of circuit verification issues. The tool features automated, intelligent execution heuristics engineered to help users seamlessly navigate between a complete Calibre nmLVS signoff flow and Calibre Recon selected circuit verification checks.

With advanced options for data partitioning, design breakdown, data reuse, task distribution, and error management, the Calibre nmLVS-Recon flow can be used with any foundry/integrated device manufacturer’s (IDM) Calibre sign-off design kit “as is”, and on any process technology node.

A vice-president at the design enablement team at Samsung Electronics, Jongwook Kye, said the new tool establishes an entirely new paradigm for circuit verification use models. He commented, “By combining the Calibre nmLVS-Recon technology with Samsung’s existing certified sign-off Calibre nmLVS design kits, our mutual customers will experience faster iterations on early ‘dirty’ designs, driving accelerated LVS verification cycles. All of this will help mutual customers tape out sooner at Samsung.”

Improving design readiness

Many product developers are today constantly striving to quickly produce more innovative, more powerful, more power-efficient, energy saving, smaller, multi-tasking SoC designs. To meet aggressive market schedules, SoC designers often have to rush to start their chip integration before individual blocks are complete or even available.

This approach is very different from traditional design cycles where blocks were designed, routed, finalized, and verified before chip-level integration took place. Engineers now don’t have the luxury of time anymore, which forces design and verification activities to happen in parallel, with many not willing or able to wait until a chip is complete and DRC-clean before running full-chip LVS verification. This considerable change in the design and verification cycle has introduced many challenges to the chip-level verification stage.

One key factor affecting the overall turnaround time of the complete verification cycle is design readiness. A design in the early stages of implementation and assembly will always be “dirty,” meaning it contains many design issues that exist solely due to its incomplete status. Running a full LVS verification cycle on dirty designs generates thousands, or even millions, of errors that must be analyzed and debugged, increasing the full-chip verification time and requiring more hardware for extensive analysis and computation parallelism.

While these designs will move towards readiness over time, which will eventually reduce the overall LVS runtime to hours, the number of time-consuming iterations that precede this milestone have already wreaked their havoc on delivery schedules, according to Mentor.

The premise of the Calibre nmLVS-Recon is to separate an iterations-based use model from the full LVS signoff use model, while allowing engineers to easily navigate between these use models without spending CAD resources or requiring foundry deck changes. The tool’s flow significantly accelerates circuit verification iterations by providing feedback that enables them to quickly analyze, fix, and verify selected design issues. Options include:

  • Categorization: focusing on specific types of violations
  • Prioritization: addressing the most impactful errors first
  • Task Distribution: enabling teams to focus on a specific set of design issues
  • Partitioning: splitting data for easier debugging and root cause analysis
  • Data Reuse: incremental execution on existing database and disk files
  • Interactive approach: on-the-fly edits to verify resolution, consolidate fixes, and speed up the debugging cycle

The Calibre nmLVS-Recon solution claims to introduce a more intuitive approach to early-stage circuit verification to execute only those checks required to solve the highest-priority issues. Engineers can easily toggle between different configurations and decide which issues they want to focus on in every round of execution. The Calibre nmLVS-Recon process automatically determines which circuit verification requirements must be executed for maximum efficiency.

The Calibre nmLVS-Recon initial offering is available to the market with the Calibre family release this month (July 2020), with planned additional capabilities in later releases.

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