New twists on MRAM design - Embedded.com

New twists on MRAM design

LAKE WALES. Fla—On the 20th anniversary of its invention at IBM Research, fabled nonvolatile “universal” magnetic random access memory (MRAM) is getting an upgrade. IBM announced that, in collaboration with foundry-giant Samsung, it is using a spin-transfer torque (STT) design on its MRAM.

Faster than flash and as dense as dynamic random access memory (DRAM), this universal memory genre is now being readied for manufacturing with a final round of material optimization and engineering finesse at IBM (Yorktown Heights, N.Y.). IBM says its STT MRAM access clocks at 10 nanoseconds and ultra-low-power (7.5 microamps), claiming its MRAM outperforms flash at the speed of DRAM. Applications include everything from tiny Internet of Things (IoT) system-on-chips (SoCs) to vast mass storage systems for servers.

20 years in the making
“IBM has been working for 20 years on the magnetic random access memory, or MRAM, starting from a DARPA [Defense Advanced Research Project Agency] funded research project, along with Motorola, on field-switched MRAM,” Daniel Worledge, lead researcher, distinguished research staff member and senior manager of MRAM at IBM Research (Yorktown Heights, N.Y.) told EE Times. “IBM's John Slonczewski invented the spin-torque switching method for MRAM back in 1996, but at first we thought the field-switched method was best.”

“We switched to the spin torque technique after a DARPA-funded research project with Motorola. Now we are celebrating its 20th anniversary after having scaled down the design to 11-nanometer in collaboration with Samsung,” said Worledge.

Worledge does not believe that IBM's STT MRAM will replace DRAM anytime soon but believes it can replace embedded flash, since SST MRAM is easier to embed, faster and has unlimited reads and writes, unlike flash which is typically limited to 10,000. Next IBM plans to optimize the cell's engineering parameters, for mass production with a partner in as little as three years.

Each bit-cell of a spin transfer torque (STT) magnetic random access memory (MRAM) contains one transistor and one tunnel junction arranged vertically.  The tunnel junction is composed of a fixed magnet whose north pole always points up, and a free magnet whose north pole points up or down depending on whether it is storing a '0' or '1', respectively. It is programmed by merely passing a 7.5 microamp current through it in the direction of desired polarization.(Source: IBM)

Each bit-cell of a spin transfer torque (STT) magnetic random access memory (MRAM) contains one transistor and one tunnel junction arranged vertically.  The tunnel junction is composed of a fixed magnet whose north pole always points up, and a free magnet whose north pole points up or down depending on whether it is storing a '0' or '1', respectively. It is programmed by merely passing a 7.5 microamp current through it in the direction of desired polarization.

(Source: IBM)

A transmission electron microscope (TEM) image of a single 11-nanometer junction of IBM's spin-transfer torque (STT) magnetic random access memory (MRAM).(Source: IBM)

A transmission electron microscope (TEM) image of a single 11-nanometer junction of IBM's spin-transfer torque (STT) magnetic random access memory (MRAM).
(Source: IBM)

The biggest challenge that the IBM/Samsung overcame was building a vertically oriented cell.

“We knew back in 2009 that to scale as well or better than DRAM we had to have a vertical magnetic cell, just as DRAM has to have a vertical capacitive cell,” Worledge told EE Times. “But it took our earlier collaboration with TDK to create the vertical architecture. We also partnered with Micron briefly, which continues to work on MRAM, but it took our partnership with Samsung, which had its MRAM Forum at out Zurich Lab last week, to scale the vertical architecture down to 11-nanometers with a clear path to 10-nanometers.”

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