LONDON — Aeroflex Gaisler AB has released the LEON4 licensable 32-bit processor core based on the SPARC V8 architecture.

The processor is available as a soft core together with a IP library (GRLIB) for instantiations into both FPGAs and ASICs.

It is targeted at high-end industrial and consumer electronics applications and supports symmetric and asymmetric multiprocessing.

“The power and size optimized LEON4 is fully software compatible with previous LEON processors, yet with a performance increase of up to 50 percent at the same clock frequency,” said Jiri Gaisler, CTO and Founder of Aeroflex Gaisler (Gothenburg, Sweden).

LEON4 implements single-cycle load/store instructions, as well as static branch prediction. The register file and internal load/store data paths have been extended to 64-bits, while the data cache and bus interface can be either 64- or 128-bit wide.

An optional Level-2 (L2) cache has also been added to the architecture, further improving performance on data intensive and multi-core applications. The LEON4 processor delivers up to 1.7 DMIPS per MHz or 0.35 SPECINT2000/MHz.

Aeroflex Gaisler AB

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