NEWS: Atmel aims to undercut ASIC SoCs/FPGAs with $75K NRE customizable MCU - Embedded.com

NEWS: Atmel aims to undercut ASIC SoCs/FPGAs with $75K NRE customizable MCU

San Jose, Ca. – At the Embedded Systems Conference here, Atmel (Booth 316) took the wraps off its newest CAP7L metal customizable MCU that allows ARM7-based SoCs to be implemented with 12 week turn-around, a nominal NRE charge of only $75,000, and unit costs as low as $5, including the ARM-license.

According to Jay Johnson, Atmel's director of CAP marketing, comparable low-volume SoC implementations typically have up front license fees for the ARM core that start at $100,000, as well as unit costs of $100 or more.

In contrast, CAP7L SoCs are economical in volumes of 10K units, with a $18 fully-amortized unit cost. In 50k unit volumes, the amortized unit cost is only $7, including NRE and IP license.

AT91CAP7L devices are standard product microcontrollers with up to 200K gates of metal programmable cell fabric that can be used to implement proprietary customer IP, hardware accelerators, additional processor cores or unique peripherals sets to achieve a customized SoC.

He said this newest implementation with a bargain-basement $75K NRE is made possible by Atmel's second-generation metal programmable cell fabric technology, MPCF-II.

“The original MPCF technology, announced in 2007, achieved the silicon efficiency of cell-based ASICs with the lower cost and quicker turn-around of platform ASICs,” said Johnson. “The original recipe used contact, six metal, and five via layers for the MP Library cell configuration and interconnect.

“The new MPCF-II technology has a new VP (Via Programmable) cell library designed to configure and route the chip using only three metal and three via layers, thereby reducing the number of masks to modify from 12 to just 6 and cutting NRE costs by 50%.”

The metal programmable (MP) block comprises about 15% of the CAP7L die area. The remaining 85% of the die is pre-defined, consisting of an ARM7 core with 4-layer AHB bus and 22 channel peripheral DMA controller, USB device, SPI master and slave, two USARTs, three 16-bit timer counters, an 8-channel/10-bit analog to digital converter, 160 Kbytes of SRAM, plus a full-functioned system controller including interrupt, power control and supervisory functions.

To ensure adequate communication between the custom functionality in the MP block and the rest of the chip, the metal programmable (MP) block has two AHB masters and two AHB slaves, fourteen advanced peripheral bus (APB) slaves, and 32-bit programmable I/O that may be hardware selected to share I/O. An on-chip priority interrupt controller provides up to 13 encoded interrupts and two additional un-encoded interrupts for DMA transfers.

“Fabless semiconductor companies are often stuck between a rock and a hard place when it comes to implementing new designs,” said Johnson. “The $500,000-plus NREs and million-unit minimum order quantities for full-custom ASICs are prohibitive ” particularly when market acceptance is uncertain.

While low-volume, quick-turnaround ASICs are available, they typically have unit costs of hundreds of dollars. Although some do not carry mask charges, they do require the purchase of an ARM IP license, which can cost in excess of $100,000.

The remaining option is an FPGA with embedded soft core or external microcontroller, he said. But the problem with this approach is that it has worse performance characteristics, a larger footprint, and consumes 44-times more power than an integrated SoC.

In addition, the “secret sauce” implemented in the FPGA is vulnerable to theft. In many cases, it is not an option. “Fabless semi companies can not go to market with an FPGA solution,” he added.

“The CAP7L customizable microcontroller provides an affordable low-volume solution with the power consumption, performance characteristics, and IP security of a custom-SoC, without excessive license fees or units costs. Worst-case static power consumption for the CAP7L is between 3mW and 4mW ” 98% less that the power consumed by a typical FPGA,” Johnson said.

The design flow for the CAP7L is the same as it would be for an FPGA-plus-MCU or ASIC implementation. The design is initially developed using an Altera or Xilinx FPGA and an ARM7 MCU. Atmel's provides the CAP7E ARM7-based MCU with direct FPGA interface for this purpose.

The interface on the CAP7E affords the FPGA direct access to the AHB and peripheral DMA controller on the CAP7L. Atmel also provides FPGA logic that decodes and encodes the bus traffic that flows between the FPGA and the CAP7E microcontroller. The logic blocks inside the FPGA are connected to the CAP7E via the AHB master and slave channels.

The CAP7E-plus-FPGA implementation can be used for early market testing and proof-of- concept, prior to migrating to the CAP7L.

In addition to providing the ARM core, Atmel has a large library of license- and royalty-free IP that has been fully verified and tested in the CAP7L MP block. The HDL code for any custom-IP is developed using standard, vendor-specific or third-party FPGA design tools. Once verified, the customer need only provide the register transfer level (RTL) netlist to Atmel for implementation in the MP block on the CAP7L.

Prototypes are available within 10 weeks of final gate level netlist and production quantities within 12 weeks.

The new CAP7L customizable MCUs are available now. NRE is $75K, with unit costs of $5.50 in quantities of 50k units. Turn-around time is less than 12 weeks. CAP7E MCUs with built-in FPGA interface are available now and are priced at $9.50 in quantities of 10K units.

To learn more, go to www.atmel.com.

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