Verum Software Technologies BV (Waalre, Netherlands) has received a European patent for its Analytical Software Design (ASD) technologies. The patent (# EP1749264) recognizes a method of applying the formal methods technique called communicating sequential processes (CSP) algebras to develop defect free software architectures and software codes which are event driven and exhibit lots of concurrency.
Verum believes that in the past, software architects were not able to enjoy the benefits of formal methods as they were deemed too difficult to learn, understand, and too expensive to apply and maintain for common code bases.
The ASD patent describes an integrated model based tool which allows software development experts to produce formal specifications and verified system designs that fully integrate into existing conventional software development processes. Fully integrated in this context means that there are continuous feedback loops into the software development process for handling errors extensions and modification arising in standard software development processes.
A typical process (shown below) highlights the functionality of ASD in such a process. The gap between the formal specifications and designs produced using ASD and the rest of the software development cycle is bridged for the first time. The consequence of this is that traditional errors made during requirements analysis, architecture specification and design, component specification and design are prevented from reaching the implementation, testing, and integration phases of software projects.
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The role of ASD in model based software development processes. The yellow boxes represent outputs from Verum's patented technology.
“Hardware logic designers have long enjoyed the benefits of electronic design automation (EDA) tools enabling them to verify complex designs before implementation,” said Guy Broadfoot, the co-inventor of ASD, and Verum's C.T.O. “ASD is a major step towards the goal of software design automation (SDA), being the first tool chain to make software design time verification a routine reality for software engineers. The patent grant is a very exciting milestone for Verum recognising as it does the unique contribution of Verum in this field.”
The ASD patented technology is made available to users via an integrated desk top application called ASD:Suite. The application is shown below. Users build proprietary models via a desktop client protecting their IP, and check these models using the patented ModelChecker technology which runs on Verum's servers.
Once this step is complete, another patented component, the ASD CodeGenerator, automatically generates source codes in a variety of commonly used programming languages (C, C++, Java, C#) from the verified designs. This is a crucial part of the invention as it ensures that no human errors are introduced into the verified designs and it vastly speeds to process of generating production quality code.
Verum says that its customer base using ASD includes Philips Medical Systems, Bosch, Assembleon, Logica, and FEI. Most projects involve generating tens or hundreds of thousands of lines of codes mathematically proven to be defect free Verum employs a team made up of formal methods, embedded software architects, and embedded software tools experts to develop its tools. The company also provides consulting support.