Novel FPGA family boosts performance, lowers cost -

Novel FPGA family boosts performance, lowers cost


Anyone with a spare garage can start a semiconductor company these days, but it takes a special kind of chutzpah to tilt against the FPGA establishment. After all, writing place & route software is no walk in the park, and having enough good FAEs to hold customers’ hands can be a challenge. And of course there’s the silicon itself. It’s not easy to differentiate your product given the wide range already available, albeit from a small pool of manufacturers.

Enter Efinix , with their Trion FPGA family. From the start, Efinix decided to target cost-sensitive applications, though the top of the line chip is no slouch, at 150 kLEs (plus 8 Mb RAM & 500 multipliers). At the bottom is a mere 4 kLE part, with six more sizes in-between those. You’ll also find varying numbers of PLLs, LVDS & GPIO pins, DDR3 & MIPI interfaces, and even PCIe on the top two chips.

Does Trion have any truly distinguishing characteristics? Any sort of secret sauce? Why, yes it does. While most FPGAs consist of a sea of LEs (logic elements) criss-crossed by routing channels, Efinix’ parts are all saltwater . Each LUT cell within an LE can function as either a LUT, or…a routing grid. Efinix claims this provides a four-times improvement in PPA (power, performance, area) over traditional architectures. Given they’re using an older 40 nm process, yet can wring 200+ MHz performance out of the silicon, they might be onto something.

Trion design software accepts Verilog and VHDL, and internally, uses 3rd -party compilation & synthesis modules, meaning Efinix could focus development effort on integration and place & route code specific to their architecture.

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