NPL seeks partners for lead-free reliability project - Embedded.com

NPL seeks partners for lead-free reliability project

LONDON — The National Physical Laboratory is shortly to start a studio project on the reliability of using existing substrates in a lead free process and is looking for potential partners, especially manufacturers with high reliability concerns, as well as printed circuit board and laminate suppliers.

The project will include investigation of the reliability of microvias, non functional pads and the design/build aspects of the substrate. The project will also investigate these substrates in terms of conductive anodic filamentation (CAF) susceptibility.

Following lead-free processing circuit boards will be stressed using both thermal cycling and an electrical test method. The electrical test method is an Interconnect Stress Test (IST) that is fast, environmentally friendly and includes automatic data-logging.

The test vehicle design will also include board supplier properties and NPL and its partners will design a test vehicle and carry out reliability tests to come up with a new test method for assessing circuit boards with a lead-free profile.

It is intended that the project starts within 3 months and be completed within 9-12 months. Potential partners from those companies with high reliability concerns, board and laminate suppliers should contact Dr. Chris Hunt.

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