NXP adds quad-SPI interface to ARM Cortex-M3 MCU - Embedded.com

NXP adds quad-SPI interface to ARM Cortex-M3 MCU

The LPC1800 ARM Cortex-M3 microcontroller from NXP Semiconductors is optimized for low power operation from low frequencies up to 150MHz maximum performance from either flash or RAM.

The flexible dual-bank 256-bit wide Flash memories can be used for concurrent write/read operations, allowing 'golden copy' preservation and prevention of reprogramming mishaps, or simply used as a single bank of memory.  The LPC1800 also features two additional peripherals: a flexible quad-SPI interface and a state configurable timer subsystem.
 
Designed using NXP’s ultra low-leakage 90nm process technology, the LPC1800 has the  largest on-chip SRAM for a Cortex-M3 with up to 200-KB provided in multiple banks, each with separate bus master access for higher throughput and individual power-down control for low power operation.  The dual-bank 1-MB flash architecture provides the highest reliability in-application re-programming, and allows for non-stop flash operation.

NXP is taking advantage of the rapid adoption of quad-SPI architectures in newer serial flash memories to provide a seamless high-speed interface that will connect with virtually all SPI and quad-SPI manufacturers. High-speed interfacing from quad-lane SPI memories at up to 80 Mbps per lane provides for larger off-chip data and code execution than available from on-chip memories.
 
The LPC1800’s state configurable timer subsystem comprises of a timer array with a state machine enabling complex functionality including event controlled PWM waveform generation, ADC synchronization and dead time control. This timer subsystem gives embedded designers increased flexibility to create user-defined wave-forms and control signals for many applications including power conversion, lighting and motor applications.

Additional peripherals available on the LPC1800 include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware enabled TCP/IP checksum calculation, a high-resolution color LCD controller, and AES decryption including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request.
 
Standard features on all members of the series include 32-KB ROM containing boot code and on-chip software drivers, eight-channel General-Purpose DMA (GPDMA) controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor control PWM and quadrature encoder interface, 4 UARTs, 2 fast-mode Plus I2C, I2S, 2 SSP/SPI, smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers and up to 80 general purpose I/O pins.
 
The LPC1800 is available in 144-pin and 208-pin LQFP packages and 100-pin, 180-pin and 256-pin BGA packages. Flash-based LPC1800 engineering samples are available now. Flashless LPC18x0 parts, featuring larger on-chip SRAM, are sampling now and will be available through distribution in December.

Additional information on the LPC1800 is available here.
 
 

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