NXP mixes Cortex-M4, M0 in dual core attack - Embedded.com

NXP mixes Cortex-M4, M0 in dual core attack

The LPC4000 family from NXP Semiconductors is a asymmetrical dual-core digital signal controller architecture which includes both ARM Cortex-M4 and Cortex-M0 processors.  The company plan to feature it next week at both the ARM TechCon in Santa Clara  and Electronica in Munich.

The dual core approach will enable the development of DSP and MCU applications within a single architecture and development environment.

With this dual-core architecture and a set of configurable peripherals, the LPC4000 should enable the development a range of applications such as motor control, power management, industrial automation, robotics, medical, automotive accessories and embedded audio.

 
The NXP LPC4000 family has an Cortex-M4 processor which combines the benefits of a MCU – integrated interrupt control, low power modes, low cost debug  – with high-performance digital signal processing features such as single-cycle MAC, single instruction multiple data (SIMD) techniques, saturating arithmetic, and a floating point unit.

It has an optimized 256-bit wide flash memory architecture which reduces power consumption with minimum memory fetches while maximizing the performance of the Cortex-M4 processor. The LPC4000 has a dual bank architecture that provides up to 1MB flash for safe re-programming and flexible memory partitioning. The LPC4000 offers 264 KB SRAM, making it the largest available on any Cortex-M microcontroller.

The Cortex-M0 subsystem processor offloads many of the data movement and I/O handling duties that can drain the bandwidth of the Cortex-M4 core. This allows the Cortex-M4 to concentrate fully on crunching numbers for digital signal control applications. Having an asymmetrical dual-core gives access to the power, cost and system complexity savings of a one-chip solution – and allows easier partitioning of software.

The configurable peripherals available on the LPC4000 include a state configurable timer, an SPI flash interface, and a serial GPIO Interface.

The state configurable timer subsystem consists of a timer array with a state machine enabling complex functionality including event-controlled PWM waveform generation, ADC synchronisation, and dead-time control.

The SPI flash interface provides a seamless high-speed memory-mapped connection to virtually all SPI and quad-SPI manufacturers.

NXP’s serial GPIO is available for the first time on the LPC4000 and provides the flexibility to interface to any non-standard serial interface or to mimic multiple standard serial interfaces (such as I2S, TDM for multi-channel audio, I2C and more).

Additional peripherals on some members of the family include two HS USB controllers, an on-chip HS PHY, a 10/100T Ethernet controller with hardware-enabled TCP/IP checksum calculation, and a high-resolution color LCD controller.

Standard features on all members of the LPC4000 family include 32 KB ROM containing boot code and on-chip software drivers, AES-128 decryption (encryption is available on some members of the family), eight-channel general-purpose DMA (GPDMA) controller, two 10-bit ADCs and 10-bit DAC with data conversion rate of 400k samples/s, a motor control PWM and quadrature encoder interface, 4 UARTs, 2 Fast-mode Plus I2C, I2S, 2 SSP/SPI, smart card interface, 4 timers, windowed watchdog timer, an alarm timer, an ultra-low power RTC with 256 bytes of battery powered backup registers, and up to 146 general purpose I/O pins.

A free C Library of optimized DSP algorithms for the Cortex-M3 and M4 will be made available including FFT that supports both 32 and 16 data lengths and block sizes of 64, 256 and 1024 and well as FIR and IIR filters with 16-bit single stage Biquad and 32-bit single stage Biquad. Also included with be a PID controller, resonator function, random number generator,  dot product
and cross product of vectors.
 
NXP Semiconductors provides ARM Cortex-M0, Cortex-M3 and Cortex-M4 microcontroller families and the LPC4000 is the only Cortex-M4-based controller to have a pin-compatible Cortex-M3-based equivalent.


NXP Cortex-M4 roadmap

Engineering samples of the NXP LPC4000 will be available at the end November, with full commercial distribution starting in December 2010.

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