The 1-wire bus is simple and inexpensive. Hardware and softwareprocessor-interfacing techniques are described here.
Dallas Semiconductor's 1-wire bus is an inexpensive method of adding local and remote peripherals, hardwired electronic serial numbers, and non-volatile storage. The 1-wire bus only requires a single bi-directional I/O pin to implement, has extremely flexible electrical interface requirements, and very forgiving timing requirements. The wide variety of standard devices with this interface makes it attractive for a number of applications. Table 1 describes a few of the possibilites.
Table 1: 1-wire applications
48-bit built-in serial number
Firewire serial number device
Write once devices
Add ports a bit at a time
All 1-wire devices provide the ability to serialize products. Each device has a unique 48-bit serial number that provides a unique address. This number can be used to serialize a printed circuit board. In addition, some 1-wire devices provide a read-only memory that contains a pre-assigned serial number that can be used for a Firewire or Ethernet MAC address. A variety of 1-wire devices provide EE-PROM or write-once memory that can be used for non-volatile storage.Dallas also manufactures a 1-wire interface A/D converter device. This provides up to 16-bit resolution with up to eight bits of accuracy with internal voltage references. Each of the four A/D input channels may also be used as a digital input or output, making this device and the single bit 1-wire I/O port ideal for remote sensing applications.
In one incarnation, 1-wire devices are available in a format referred to as the I-button. I-button devices are packaged in a case similar to a coin cell battery. These devices are small, inexpensive, and very rugged, making them ideal for identification of personnel in security applications or tracking the location and status of equipment that may not normally be associated with electronics devices.
The 1-wire thermometer is ideally suited for applications requiring temperature sensing at remote locations or in electrically noisy environments that make the use of analog temperature measurement difficult.This article is divided into two major sections: hardware interfaces and software interfaces. In the first section I will discuss the electrical specifications, timing requirements, and several example implementations. In the second section I will discuss the structure of the 1-wire protocol, the software required to send and receive data on the 1-wire bus, error checking, and how to identify specific devices on the 1-wire bus.
The 1-wire bus is a master/slave protocol with a single bus master. The protocol has no provision to support more than a single bus master. In general, 1-wire devices are integrated devices supplied by Dallas Semiconductor and the bus master is a user-defined microprocessor or microcontroller. Figure 1 shows a typical configuration for a 1-wire master and device.Note that the connection on both the master and device side are open drain and that the device side has a provision to operate on parasitic power pulled from the bus itself. This arrangement allows 1-wire devices to operate with a single data/power conductor and ground, hence the moniker, 1-wire bus. The open drain configuration and fixed internal timing limit the maximum speed of the bus to approximately 16Kbps. Because of this limitation, message lengths are kept to a minimum whenever possible.All 1-wire devices are rated to operate over a wide voltage range (2.2V to 7.0V) with parasitic power. EEPROM devices, A/D converters, and temperature sensors will operate off of parasitic power, but require either a strong pull-up (less than 100 ohms) or an optional separate power supply for certain operations.
Internal timing for 1-wire devices is based on patented “silicon timed circuits” in each device. Each data exchange begins when the bus master issues a reset pulse and waits for the device or devices on the bus to respond with a presence pulse.
Figure 2 shows the timing required to reset all of the devices on the 1-wire bus. Initially the bus master pulls the bus low for at least 480s. Within 60s of releasing the bus, each 1-wire device that recognizes the reset pulse will issue a presence pulse, pulling the bus low, for at least 60s. Since all 1-wire devices are configured as open drain outputs, the bus provides a wired-or presence function.
Figure 3 shows the timing required to write either a one or a zero to a 1-wire device. The bus master writes a zero bit to the bus by driving the bus low for at least 60s. A one is written by driving the bus low for less than 15s. Note the trc element of the timing. This is due to the cumulative capacitance of the transmission line, bus master, and devices being charged through a pull-up resistor. Reliable operation of the 1-wire bus requires consideration of this effect for all but the simplest configurations.
The timing required to read each bit transmitted from a Device to the bus master is also controlled by the bus master. Figure 4 shows the timing required to read bits from the 1-wire bus. The bus master requests a bit to be transmitted by pulling the bus low for a short period, then releasing it. If the device is transmitting a zero, the device will hold the bus low for at least 15s. If the device is transmitting a one, it will not hold the bus low, allowing the bus to return to the pull-up level immediately.The selection of a pull-up resistor determines the time constant trc. This is the amount of time required for the voltage on the bus to rise to VIhmin (2.0V). The value of this parameter should be less than 15s for reliable operation of the bus. Dallas recommends the use of a 4.7 resistor for pull-up in most applications. The use of a 1.5 resistor will allow the use of up to 99 devices on 1,000 feet of Cat 3 cable. When using long cables or a large number of devices it is a good idea to compute the required maximum value of this resistor to ensure reliable operation.
A 1-wire bus can be implemented in several different ways. Each implementation and its resource requirements are discussed in the following sections.
Single I/O port
Figure 5 shows schematically how to implement a 1-wire bus using a single I/O port on the bus master to both read and write data. In this example, the microcontroller is a Scenix SX28AC. This implementation requires that the selected I/O port bit be capable of operation in either a tri-state or open drain configuration. If the bit is tri-stated (most common configuration for an I/O port), programmers can save instruction cycles by setting the output value permanately to zero and switching the tri-state control bit to select either a high or low state on the output. For this configuration to be effective the software must be capable of creating delays of 1s or less and interrupt routines must not steal more than 1s or 2s of time while a bit is being read or written, respectively. In most cases, this is accomplished by disabling interrupts during the critical timing portions of any bit read or write. The disadvantage of this type of implementation is that interrupts will be disabled for up to 60s each time a bit is read or written. The principle advantage of this configuration is the requirement for only one I/O port, leaving as many pins as possible available for other types of I/O.
Timer and capture register
When interrupt latency proves to be a critical issue, using a timer output and capture register may provide the solution. The requirement to use this type of configuration is the ability to set a timer output to turn on an output bit for a length of time programmable from 1s to 480s. The timer controlling the output bit must be capable of 1s resolution or better, up to at least 960s. An input that controls a capture register must be associated with the same timer and capable of recording the timer value on the rising edge of the input. The disadvantages of this configuration include the dedication of a timer and capture register pair to the operation of the 1-wire bus. These devices are often used in DSPs and microcontrollers for PWM transmission and reception. figure 6 shows the typical configuration of this type of implementation.
Using an optically isolated connection, like the one shown in figure 7, is often useful. This provides a method of connecting I/O devices to systems that do not have a common ground reference. Optical isolation requires the use of two I/O bits like the timer/capture configuration shown. It does not require the use of a timer output and capture register pair if you're using the same timing methods described previously in the single I/O bit configuration.
When all other attempts to provide the timing and interface bits for the 1-wire bus fail, a standard UART can be used. The interface circuit shown in figure 8 is for the logic level connections to the UART, not RS-232 levels. If RS-232*level inputs and outputs are used, a level translation device such as the MAX-232 must be placed between the I/O pins and the bus interface shown. To utilize this method of interface to the 1-wire bus, the UART must be capable of operation at 115,200bps and 9600bps. To send a reset pulse and detect a presence pulse, the data rate is set to 9600bps and the value 0xF0 is transmitted. If the value received is 0xF0, then no presence pulse was detected; if it is any other value, a presence pulse was detected and active 1-wire devices are on the bus.To send data bits, the data rate is set to 115,200bps. Sending the value 0x00 will send a one bit to the bus. Sending the value 0xFF will send the value zero to the bus. When transmitting, a word will be received by the UART for each bit transmitted. This word should be read and discarded. To receive bits, the value 0x00 will be transmitted. If the word received is equal to 0xFF, then the received bit was a one; otherwise it was a zero.
Identification -One common use of 1-wire devices is to provide serial number and configuration information for a printed circuit board. This allows a device to be aware of its own serial number and read and modify non-volatile configuration information. In a production environment it is often not enough to have the board know its own serial number. It is also important to be able to read the serial number even if the board is not functioning properly. Figure 9 shows how a 1-wire device can be configured so that it can be read by an external reader even if no power is available to the board under consideration.In some cases a 1-wire bus will have multiple devices of the same type on the bus. Each device has a unique serial number and eight bits of that serial number identify the type of device. Unfortunately, we can't know in advance which serial number belongs to which physical device when the device types are identical. To deal with this situation, a special 1-wire device, the DS2409 can be used, as shown in figure 10. The DS2409 has a 1-wire bus input and two 1-wire bus outputs. Each output bus can be individually connected to the input bus. With this device in place, like devices can be split on binary trees. When identification of each device is completed, they can be bussed back together.
The structure of the 1-wire protocol is shown in figure 11. All communications begin with a reset/presence pulse sequence. This ensures that all devices are listening and synchronized. Immediately following the reception of a presence pulse, the bus master will send a ROM Function Command, which is used to provide addressing information for the bus.
The primary ROM Function Commands include Read ROM, Skip ROM, Select ROM, and Search ROM. The Read ROM function is primarily used to determine the serial number of a 1-wire device when it is known that only one device appears on the bus. When the Bus Master issues a Read ROM command, the 1-wire device connected to the bus will respond with its 48-bit serial number. After transmission of the serial number, the accessed device is ready to receive a Memory or Control Function Command.
The Skip ROM function causes all devices to be ready to receive a Memory or Control Function. This command is used to speed up transmission if there is only a single device on the bus by avoiding transmission of the 48-bit serial number at the beginning of each communication cycle. It can also be used when multiple A/D converters or temperature sensors are present, to force all devices to begin the conversion process simultaneously.
The bus master follows the Select ROM command with the 48-bit serial number of a 1-wire device with which it wishes to communicate. After reception of the Select ROM command and serial number, only the selected device will respond to the following Memory or Control Function Command.The Search ROM command is used to determine the serial numbers of all devices connected to the bus. This command will be discussed further later.Memory and Control Function Commands provide device-specific commands such as read or write scratch pad memory, convert, set/clear output bit, and so on. Refer to specific 1-wire device data sheets for specific functions.
Sending and receiving bitsAll transmission on the 1-wire bus is LSB first. The timing for each bit must comply with the timing presented in figures 3 and 4. The timing between bits is not critical.
One bits are transmitted by holding the bus low for less than 15s. Note that in practice, a one bit is generally produced by holding the line low for approximately 1s. This is usually done because the open drain nature of the bus requires a relatively long time to return to a high voltage level after the line is released.
Zero bits are transmitted by holding the bus low for at least 60s. Bits must be spaced at least 61s apart (leading edge to leading edge). There is no specified maximum time between bits.
Data is read from the device when the Bus Master places a one bit on the bus to define the start of a receive bit time. If the addressed device is attempting to transmit a one, the device will leave the bus tri-stated and the bus state will return immediately to a high state. If the device is attempting to transmit a zero, it will hold the bus at a low for at least 30s. In essence, a bit is read by holding the bus low for approximately 1s, then reading its value between 14s and 29s later.
This section describes an example implementation of the Dallas 1-wire protocol. The examples do not perform CRC or other error checking, to keep them simple and clear. Examples of both single I/O port and capture register/timer implementations are included. The ultimate object of these routines is to provide several fundamental functions for use by higher level routines to implement the 1-wire protocol. This will allow high level routines that communicate with particular 1-wire devices to be ported with little effort to platforms that use different I/O methods to the 1-wire bus. These common routines include:
- ow_reset()-performs bus reset and presence pulse detection
- ow_read_bit()-writes and reads a single bit on the 1-wire bus
- ow_read_byte()-reads an 8-bit byte from the 1-wire bus
- ow_write_byte()-writes an 8-bit byte to the 1-wire bus
In addition to the above functions, the single I/O port method also requires the function ow_delay() which provides delays of 1s to 960s in increments of 1s. The capture register/timer implementation requires the implementation of the function ow_read_var(), which provides bit read and write timing.
Single I/O port function implementation
An example implementation of the ow_delay() functions is shown in Listing 1. This function will have to be modified for each individual hardware platform to match the specific architecture, but the fundamental concepts remain constant. Initially, the timer is placed in a hold mode so that counting is stopped. The number of microseconds for the desired delay is then scaled appropriately to the rate at which the counter will decrement when running. Finally, the counter is started in a “count down” mode and the routine stays in a tight loop until the count reaches a zero value.
An example of the ow_reset() routine is shown in Listing 2. This routine assumes that there is a register that can be used to write a one or a zero to be output and that the bit being controlled has been previously set to zero. The register portx_ctl is assumed to control whether the output bit is enabled for output or tri-stated and accepting input values in the register portx_val. This function implements the timing for a reset pulse, then waits 75s before checking for the presence pulse. The routine then waits an additional 405s to complete the required timing interval for the reset/presence pulse signals. If the return value is zero, a presence pulse was detected.
An example of the ow_read_bit() routine is shown in Listing 3. This routine makes the same assumptions about I/O registers as described previously. This routine takes a zero or non-zero input value to represent a zero or a one to be transmitted. When a one is transmitted, a read is also executed and the resulting one or zero. The routine then delays an additional 45s if the transmitted bit was a one, to ensure that the proper bit timing will always be met. This function can be used to transmit either a one or a zero bit. When it is used to read data from the 1-wire bus it must be called with a one as the input argument.
The functions ow_read_byte() and ow_write_byte() are simply repetitive calls to ow_read_bit() and are shown in Listing 4. Note that the data is shifted in and out LSB first. Note also that the implementation of these routines will be identical for the capture register/time implementation because the ow_read_bit() function for each works the same.
Capture register/timer function implementation
The timing method required for this method of implementing 1-wire bus timing is shown in figure 12. The concept is that an output from the timer can produce a falling edge followed by a timed rising edge. The counter will count up for the entire bit time. At the end of the bit time, the timer output is disabled. A capture register will “capture” the value in a counter when an event or edge occurs on an input. When this value is read, it indicates how many timer increments after the counter was started that the event occurs. The example in Listing 5 of the ow_read_var() functions was written for the Texas Instruments TMS320F240 and will need to be modified to suit the architecture of any other target device.
The TMS320F240 timer output can toggle when the counter value is equal to the COMPARE register. Because a low going pulse is needed, we actually have to load the COMPARE register with a time to set the output low and another time to set the output high. The 'F240 allows successive values to be loaded into a shadow register that will be loaded into the COMPARE register after the first match is met.
The other interesting note on the operation of this routine is the timing requirements for detection of the presence pulse. Since the bus returns to a high state, then is pulled down again by any responding devices, it is the second capture value that should be observed to properly detect a presence pulse.
The implementation of ow_reset() and ow_read_bit() for this method are shown in Listing 6. The use of the ow_read_var() function simplifies these functions further from what is required for the single I/O implementation.
The 1-wire protocol uses 8- and 16-bit CRCs to ensure the integrity of certain data streams. In general, the 8-bit CRC applies to short data sequences and the 16-bit CRC applies to longer data sequences (see the individual 1-wire device data sheets to determine which CRC is required in any given data exchange).Both CRCs begin computation with an initial value of zero. The polynomial for the 8-bit CRC is x8 + x5 + x4 + 1; the 16-bit polynomial is x16 + x15 + x2 + 1. It is important to note that one of the properties of a CRC is the identity rule: when a data byte or word equal to the current CRC value is shifted into the CRC mechanism, the result is always zero. This is very useful when the computed CRC value for a data stream immediately follows the data. In this case, if the algorithm continues to compute the CRC value through the byte (or word) containing the CRC, a valid test result is the value zero in the CRC register.
Two methods are presented here for the computation of CRC values: bit at a time and byte at a time. The bit-at-a-time method takes very little ROM space and is best for applications where code space is tight. The byte-at-a-time method consumes substantially fewer instruction cycles to implement at the cost of additional ROM, making it ideal for applications where performance is critical.
The code for implementing the Dallas 8-bit CRC a bit at a time is shown in Listing 7. This code assumes that the variable crc8 has been previously defined as a global variable of type unsigned char and that it has been initialized to zero before the first bit is passed through the code. As each bit is received, it is passed to the function until all bits, including the CRC attached to the data have been transmitted. If the final result in crc8 is zero, the data is good.
A similar algorithm can be implemented for the 16-bit CRC by changing the type of the CRC accumulator to unsigned short, replacing the value 0x19 with the value 0x4003 and the value 0x80 with the value 0x8000.The code for implementing the Dallas 8-bit CRC a byte at a time is shown in Listing 8. This code assumes that the variable crc8 has been previously defined as a global variable of type unsigned char and that it has been initialized to zero before the first byte is passed through the code. As each byte is received it is passed to the function until all bits, including the CRC attached to the data, have been transmitted. If the final result in crc8 is zero, the data is good. The complete table for crctab is provided in Dallas Semiconductor Application Note 27: Understanding and Using Cyclic Redundancy Checks with Dallas Semiconductor iButton Products. This application note also describes a method for implementing a 16-bit CRC using two 256-byte tables.
Polling for devices
Finding multiple serial numbers on a 1-wire bus is certainly the most difficult operation associated with this protocol to visualize. The basic process determines the serial numbers of the devices present by successively eliminating devices from a pool of answering devices using the Search ROM command. The Search ROM command activates all devices on the bus. For each bit in the 48-bit serial number, 8-bit device number and 8-bit CRC, all currently selected devices will respond to two-bit read commands. During the first bit read time slot, all devices that have a zero in their serial number in the current bit position will respond on the bus with a zero. During the second bit read time slot, all devices that have a zero in their serial number in the current bit position will respond with a zero. These two reads have four possible outcomes. If two zeros are read (B), at least one device has a zero in that bit position and at least one device has a one in that bit position as well. If the first read returns a zero and the second returns a one, the only devices remaining on the bus have a zero in the current bit position. If the first read returns a one and the second read returns a zero, then all active devices have a one in the current bit position. Finally, if both reads return a one, then there are no devices currently active on the bus.
After reading these two bits, the bus master will transmit a zero or a one. If a one is transmitted all devices with a zero in the current bit position will drop off. If a zero is transmitted all devices with a one will drop off. By selectively dropping off duplicated bit positions, eventually a full 64-bit (48-bit serial number plus 8-bit CRC) value will have been accumulated and only one device will be left active on the bus. Once a device has been found, we repeat the process, selecting different branches each time, until all devices have been identified.
Listing 9 shows an example, using 4-bit serial numbers for simplicity. When a bit position has both a zero and a one for current devices, the zero branch is selected first. Once all four bits have been identified for one device, the next iteration will duplicate the first bits sent up to the last position where both a one and a zero were detected and a zero was sent. That position is then selected as a one and the process continues for the remaining bits until there are no more duplicate bits that have been sent a zero in the previous iteration. Listing 10 contains the implementation of this algorithm.
The Dallas Semiconductor 1-wire bus is a robust and inexpensive method of system expansion and communications. The simplicity of this bus allows a great deal of flexibility in implementation over a wide variety of hardware platforms.
H. Michael Willey , vice president of Paragon Innovations Inc., has more than 22 years of experience in embedded systems design with specialized expertise in telecommunications, industrial process controls, robotics, precision-positioning systems, switching systems, and medical electronics. Willey holds a BS in electrical engineering from Texas A&M University. His e-mail address is .
- Figure 1 1-Wire master/slave configuration
- Figure 2 Reset timing
- Figure 3 Write timing
- Figure 4 Read timing
- Figure 5 Single I/O bit bus configuration
- Figure 6 Timer/capture configuration
- Figure 7 Optical isolation
- Figure 8 UART interface
- Figure 9 External reader configuration
- Figure 10 Using the DS2409
- Figure 11 Protocol structure
- Figure 12 Capture/timer timing relationships
- Figure 2 Reset timing
- Listing 1 ow_delay()
- Listing 2 Method 1 – ow_reset()
- Listing 3 Method 1 – ow_read_bit()
- Listing 4 ow_read_byte () and ow_write_byte()
- Listing 5 ow_read_var()
- Listing 6 Method 2 – ow_reset() and ow_read_bit()
- Listing 7 Byte at a time CRC8 calculation
- Listing 8 Byte at a time CRC calculation
- Listing 9 Polling example
- Listing 10 Finding serial numbers