Optimizing power consumption is an important design goal for systemsbased on digital signal processors (DSPs), but it is a goal that isoften difficult to achieve. Today, DSP-based equipments often combineapplications that were previously separate, and each application mayhave multiple operating modes. Developing a power profile for such adevice, let alone the entire complex system, is very difficult.Designers need the best information available, as well as techniquesand tools that can help them optimize power consumption within thespecific application.
Fortunately, DSP chip design and manufacturing processes havedeveloped more advanced methods for reducing power consumption inrecent years. On-chip power optimization techniques now offer moregranular control, more power-saving modes, and more completeinformation about processor power consumption than ever before. NewerDSP development tools give designers more insight into how theirsystems consume power and provide techniques for lowering powerconsumption via on-chip hardware.
And DSP operating systems incorporate power management features inorder to give developers greater control over power-saving techniquesand to coordinate low-power operation and timing among the many on-chipfunctions. When these built-in features and tools are used incombination with a well-planned system design, power consumption in aDSP system can be dramatically reduced.
Low power matters
Low power consumption is important for all DSP systems, though thereasons vary somewhat by application. In grid-powered systems, loweringthe power decreases operating expenses, increases reliability andallows compact design that permits more functionality to be packed intothe same space, with less need for fans and other cooling techniques.In critical applications such as high-definition medical imaging, heatcan even cause operating problems, thereby defeating the purpose of theequipment and reinforcing the need for low power dissipation isessential.
In portable electronic systems, low power consumption helps minimizesize and weight while maximizing the life of the battery betweencharges. Smaller batteries can be used, further reducing the scale ofthe system. Lower power also helps keep portable systems from becominghot during prolonged use. Cellphones, PDAs, MP3 players, digital stilland video cameras, electronic instruments—these and other handhelddevices can all become smaller, run cooler and operate longer betweencharges with lower power consumption.
Understanding power profiles andchip resources
The first step toward reducing power in any type of system isunderstanding how the system is used and how that usage affects powerconsumption. A cellphone, for instance, spends a great deal of its timewaiting for a call, but relatively little time during the call. An MP3player, on the other hand, is normally either on and in activeoperation, or off. Other systems, line-powered as well as portable,have different profiles of standby and active operation, as shown in Figure 1, below.
|Figure1: Active And Standby Power|
Understanding this profile can help the designer choose apower-efficient processor, since the fundamental CMOS technology of aDSP can greatly affect power consumption in a specific type ofapplication. Advanced CMOS processes are based on high-performancetransistors that run at extremely low voltages. Depending on theintended application, the transistors can be tailored either tominimize power consumption by clamping quiescent current, or tomaximize performance, though with slightly greater current leakage.DSPs designed for applications with long standby times, such ascellphones, keep quiescent current to a minimum with low-leakagetransistors, while DSPs designed for high-performance applications thatare always active favor faster-switching transistors.
System usage also involves the responsiveness of the system toevents and, thus, the latency when circuitry is powered on. Some delayis expected on initial power-up, and a lesser delay is acceptable whena system wakes from a standby mode. But users generally expectimmediate response from a system that is in active operation so thaton-chip functions cannot be too deeply asleep at these times. Twoconsiderations enter here: first, some functions can be shut down morecompletely than others, especially during standby periods, but alsoduring active operation. Second, the more granularity the processoroffers in controlling its power modes, the more the designer can tailorpower consumption to the operating profile of the system.
Power-efficient DSP chip designs take into account theseconsiderations by creating power domains that enable the application todisconnect the clock inputs to functions that are not in use. Just as aprocessing core can enter a sleep mode, where it performs no operationsuntil it is awakened by an interrupt, so peripherals and memory blockscan be put to sleep until needed. The transistors in the unclockedfunctions lose no power except for quiescent current, and the wake-updelay required for resuming the clock is minimal. As system designersconsider the usage profiles of their products, they also need to takeinto account how much control the DSP gives them, or handlesautomatically, over clocking individual functions.
An additional feature that is now built into power-conserving DSPsis the ability to scale the core voltage and frequency. If the DSP canreduce the core clock rate and still meet its processing requirements,a proportional savings in active power consumption results. And whenlower frequencies are combined with lower operating voltages, theadditional power savings can be significant. Voltages and frequenciescan be scaled at startup for all system operations, or they can becontrolled dynamically through software as the application needschange, providing an important means for cutting power consumptionduring off-peak processing intervals.
Getting the right power information
Multiple cores, applications and power modes can make estimating powerfor complex DSP systems very difficult. Traditional methods ofdetermining power were based on information such as the maximum currentfigure from the device data sheet, current draw per cycle orinstruction (mA/MHz, mA/MIPS), and test cases, often synthetic, for theentire chip.
Although useful for gross estimates, these methods are notacceptable for estimating the power consumed by a DSP in a complexsystem where the cores, peripherals and on-chip memory may be turned onand off independently according to changes in the applications andoperating modes. Designers need visibility into the power consumed bydifferent functions on the chip in real applications because realisticpower information enables them to estimate more accurately the effectsof different implementations and to determine how an applicationaffects power consumption on different platforms.
What is called for on the part of the DSP manufacturer is a modularapproach to power estimation that divides the device into subsystems,then exercises each subsystem independently. Once maximum and idlepower figures are established for each of the on-chip functions, it ispossible to create a power consumption curve for each by interpolation.Then, when the level of operation of each function is specified, theresulting power figures derived from the individual curves can besummed to provide a realistic estimate for the entire device.
Figure 2 below shows a power estimation spreadsheet that breaks down a representativeDSP into its subsystems, accepts user-supplied parameters, and returnsa device power estimate. As the spreadsheet indicates, a valid estimateis based on user-supplied information that reflects a goodunderstanding of system usage, including factors such as data width,frequency, supply voltage, and the percentage of the availablebandwidth for peripherals that is in use.
|Figure2: Power Estimation|
Designing for low power consumption
Power-conscious design techniques help the DSP developer take fulladvantage of a valid power estimate. At the system level, the designershould select components carefully and keep their number as low aspossible. In addition, the designer should consider which unusedcomponents can be powered down at times, especially during standbyoperation. Use of board-level memory is also a power drain, since ithas to energize both memory chips and board traces.
Whenever possible, the application should use the DSP's internalmemory, keeping high-bandwidth memory on-chip and reserving externalmemory for low-speed, occasional access. Off-chip memory also serveswell for booting but should be powered down after startup. Softwareshould be optimized for performance in order to reduce the code'sfootprint in memory and the number of instruction fetches. Tighter codemakes better use of the cache and internal instruction buffers, andsince it generally runs faster, it reduces the system's time in activemode.
The most device-specific power reductions take advantage of theDSP's built-in hardware capabilities. From startup on, the applicationcan idle domains that are not in use, limiting peripheral powerconsumption to only the I/Os that are needed at a given time. Normally,the application will control the domains directly at boot time, whilelater on the DSP core can run a background loop that checks forfunctions that are not needed and turns them off. If the applicationuses these techniques, the chip's sleep modes can minimize the powerdrains of the core and chip domains during idle times.
The DSP core voltage and frequency (V/F) can be scaled at boot timeif the total performance required does not equal the full capabilitiesof the device. V/F scaling can also be dynamically invoked during runtime if, say, the system alternates among applications that havedifferent performance loads. For V/F scaling, the design has to provideexternal control of the DSP's supply voltage, as well as softwarecontrol built into the background loop. Since frequency scaling slowsthe core's operation, the designer should consider the timing ofdependent operations in designing the application.
Power management in the OS
Changing the power requirements of the system dynamically, whetherthrough V/F scaling or through low-power modes, requires theinvolvement of the DSP's real-time operating system (RTOS). A powermanagement (PM) module within the RTOS implements boot-time powersavings and coordinates the various low-power operations throughout thesystem.
Core frequency scaling can affect the timing of subsystemoperations, so the PM has the capability to scale the clock after afrequency scaling operation. If the OS clock accuracy is not importantto the application or if the user wishes to conserve code space, thisPM capability can be disabled.
Additionally, the user can also enable or disable the PM functionthat automatically idles clocks when threads are blocked. In itscoordinating role, the PM provides a registry for power eventnotifications, which allows clients to register for notification whenspecific power management events occur. Because of the complexity ofthe system, the PM supports multiple client instances and allowsclients to have delayed completion of events.
The PM also exports a library of application program interfaces(APIs) that enable software control of the chip's low-power techniques.Through the APIs, the application can gate clocks, activate sleep modesand safely manage the transitions between setpoints for V/F scaling.The setpoints are parameters of scaling that allow the V/F to belowered and raised in the right sequence and with the necessary setuptimes for proper operation.
Figure 3 below shows how setpoints govern the timing of V/F scaling. Because thevoltage and frequency scaling implementation is specific to the DSP andvoltage regulator used in the design, the PM APIs support setpointlatency queries and configurations as well as the PM library can berebuilt.
|Figure3. Effects Of Scaling On Power Consumption|
Development assistance from tools
Dealing with all of these techniques effectively requires tools thatare designed for power management. Paralleling other areas of DSP tooldevelopment, power optimization tools seek to provide visibility andease of use to help simplify system analysis and speed time to market.
The tools work with the DSP's embedded and RTOS power managementtechniques while providing test features such as meters, scopewaveforms, channel calibration, test code, and event triggering, amongothers. With these capabilities in hand, the designer has a feedbackmechanism that enables evaluation of how alternate implementationsaffect power consumption.
Figure 4, below ,shows how and where in the design cycle integrated hardware and toolplatforms such as National Instrument's C55xPower Optimization DSP Starter Kit (DSK) can help developersevaluate the DSP's power consumption in different design scenarios,saving them time as they determine the best overall mix of low powerconsumption and high performance for their systems.
|Figure4. Power Optimization Flow|
Designing for power from thebeginning
Power optimization is sometimes treated as an afterthought in systemdevelopment, but it should not be. The earlier it is considered in thedevelopment cycle, the better, especially in complex systems withmultiple applications and operating modes. In handheld systems, lowpower consumption is usually a major requirement in order to extendbattery operating time, but even line-powered systems need to keep heatdissipation and operating costs down by drawing less current.
In order to optimize power consumption, a designer needs tounderstand the power profile of the system, then reference aninformation resource that takes into account all of the major systemfunctions in deriving a power estimate. DSPs that are based onpower-efficient CMOS processes integrate hardware techniques such asgranularly defined low-power modes and voltage and frequency scaling.APIs make these techniques readily available to the application forcontrol through the RTOS, and test tools help the designer evaluatedifferent implementations for power consumption. With all of theseresources available, developers have every reason to design for powerfrom the very beginning of the development cycle.
Jim Patterson is a member of the Group Technical Staff, andJohn Dixon is Worldwide C5000 Platform Marketing Manager at Texas Instruments.