Long battery life is crucial to a positive user experience in wearable devices. Research shows that the most battery power in a wearable application is consumed by the display. One approach is simply to increase battery capacity, but the required size and weight of larger batteries is not practical in wearable devices, especially as the market expands to new, smaller form factors. Increasing the challenge, advances in battery technology are not keeping up with increasing system demands. Therefore, minimizing display power consumption is a key design consideration for the wearables market.
Human visual perception is quite precise, driving the trend towards higher resolution displays in wearable devices. Various energy conservation schemes can be implemented, but any degradation in visual quality will directly affect the overall experience with the device. Therefore, care should be taken when considering energy conservation schemes for displays. Higher resolution displays require high memory bandwidth, so reducing memory power consumption in both standby and active modes is required to improve battery life.
Display system architecture
Displays consist of an array of pixels. Values driven to each pixel determine the color displayed. A RAM-based frame buffer holds the color information of each pixel in the display. Most common parallel displays require refresh cycles which read data from the frame buffer then display it on the LCD. If the resolution and color depth of the display is low, the controller’s internal RAM can be used as the frame buffer.
As displays get larger, with greater resolutions and color depths, internal RAM will not provide sufficient size or performance. Double buffering will also be required to avoid the risk of screen tearing. In these systems, it’s common to implement the frame buffer in an external memory. During the refresh cycle, data is read from the external frame buffer and output to the LCD controller data bus along with control signals. Figure 1 shows a typical LCD display with an external frame buffer.
Figure 1. Parallel SRAM display buffer implementation (Source: Cypress)
There are several ways to reduce display power.
Integrate the display controller inside the main microcontroller. Commonly available display modules have a built-in controller. Having the display controller as part of the main microcontroller helps to utilize low power features of the main microcontroller.
Use low power memory as a frame buffer. Since the frame buffer is always on, it is important to have a memory with low standby current.
Reduce frequent updates to the frame buffer. Having a sufficiently large memory and having multiple frames loaded reduces the CPU active current. If the most frequently accessed frames are loaded into memory, there is no need to load and unload data from the frame buffer. Switching the frame buffer to a different memory location can switch the images on displays.
Traditionally, Parallel Asynchronous SRAMs have been used as external display buffers since they have been readily supported by the controllers and displays. However, these memories require large packages with high pin counts. Alternatively, serial memories reduce pin count and package size, which reduce required controller pins and saves PCB cost. While operating at 108MHz in Quad SPI mode, a serial memory can meet the performance of Parallel Asynchronous SRAMs. For example, the Cypress Excelon F-RAM is a serial non‑volatile memory up to 8 Mbit density available in low pin count, small GQFN packages. The device supports four power modes to optimize power consumption. Typically, 108 MHz Quad SPI operation consumes 16 mA of active current. When the memory is not active, standby mode consumes 102 µA. Deep power mode drops consumption down to 0.8 µA and hibernate mode achieves the lowest consumption at 0.1 µA.
The availability of multiple power modes with different wake-up times enables developers to reduce total power consumption based on the application’s needs. When the display is being used, memory will be in active and standby modes based on when the memory is accessed for burst reads. When the display needs to be inactive for a short duration, deep-power down mode can be used. When the device will be inactive for a longer duration, hibernate mode can be used.
Figure 2. Cypress PSoC® 6 + Excelon F-RAM based display solution (Source: Cypress)
Figure 2 depicts a typical implementation using serial F-RAM. The CPU is responsible for writing the initial display data into the frame buffer. Once written, the LCD controller will initiate a periodic refresh of data from the F-RAM frame buffer to the LCD display. Designing with F-RAM achieves >30 frames per second (fps) for wearable displays. Typical fps which can be achieved in various display sizes with QSPI F-RAM are shown below.
|Resolution||Color Depth||Frames per Second (fps)||% Memory inactive time|
|320 x 240||16‑bit||25||0%|
Apart from the display buffer, non-volatile F-RAM can double as storage memory for pre‑rendered images, thereby freeing up Flash space. This also saves initial setup time for the frame buffer. Traditionally, data and/or display templates are copied from Flash to the frame buffer on power-up or wakeup from low power modes. Using non-volatile memory frees up the system to speed power-up time. Figure 3 shows a typical power consumption profile of a microcontroller in a display application. Maximum power consumption occurs during rendering and transfer of display images. Having pre-rendered images reduces microcontroller active time, reducing this extra power consumption.
Figure 3. Profile of microcontroller power consumption (Source: Cypress)
For the display application, 320×240 resolution and 16-bit per pixel display is used. This requires a display buffer size of 150 KB. A 4-Mbit serial F-RAM can hold 3 frames of this size. Typically, wearable displays are much smaller in size and resolution, requiring a smaller display buffer. For a display buffer, serial F-RAM is used in memory mapped mode, which allows the CPU to access serial F-RAM as any other internal memory. In this example, the display controller is implemented in a PSoC 6 using Universal Digital Blocks (UDB), Serial Memory Interface Block (SMIF), and Direct Memory Access (DMA) to achieve a low power refresh operation (see Figure 4 .) The Display Controller (UDB) will generate control signals including HSync, VSync, Data Enable (DE) and Dot Clock for display. Since the UDB has only a 4-byte FIFO, internal SRAM is used as a line buffer. The line buffer is very small compared to the frame buffer and doesn’t require large internal SRAM.
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Figure 4. Architecture of an Integrated LCD Controller with Serial Memory (Source: Cypress)
Display controller refresh rates are expressed as frames per second (fps). The start of each frame is indicated by a Vsync pulse. Within each frame there are multiple lines corresponding to horizontal display lines. The start of each line is indicated by a Hsync pulse, and data within each Hsync pulse is timed by Dot Clock as shown in Figure 5 .
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Figure 5. Display Refresh Cycle (Source: Cypress)
Before every horizontal sync pulse, a line buffer is copied from external F-RAM to SRAM by triggering a DMA. As the DMA does not require CPU intervention, the CPU to can remain in sleep mode to save power. On every dot clock, the DMA is initiated from the line buffer (SRAM) to the display controller (UDB FIFO). The display controller will output the data onto the display bus along with proper control signals. The time between the two frame refresh cycles is called a blanking period (specifically vertical blanking) which can be used to update the F-RAM frame buffer.
The total power consumption is a function of the power consumed by the CPU + frame buffer + display module. If the power consumed by the CPU and the display module remains the same across the serial and parallel memory, the difference in power consumption is observed due to different current specifications of serial F-RAM and parallel SRAM as shown below.
|Active current (mA)||Standby current (mA)||%Active current||%standby current||Energy Consumption (mW/Sec)|
|Async SRAM[ 1 ]||35||20||50%||50%||90.75|
For comparison, IS61/64WV25616EFALL is used
F-RAM provides a power advantage when compared to traditional display buffers along with lower pin count and smaller packages. F-RAM can be used as a generic frame buffer with any controller that has a built-in display controller. In addition to minimizing power consumption , F-RAM memory can also improve efficiency when used as the non-volatile storage for wearable devices (see Low Power Data Logging for Portable and Medical Applications).
The wearables market is exploding, and imaginative designers are creating ever smaller form factors. Long battery life – and hence low power consumption – is a critical success factor for consumer adoption. To achieve this, an important strategy is to minimize the display power budget. Utilizing F-RAM as an alternative to traditional SRAM display buffer implementations is a great approach.
Harsha Medu is senior staff applications engineer at Cypress Semiconductor. He has worked on design and application aspects of various non-volatile memory products and defined system solutions based on new products. He holds a Bachelor of Engineering degree in Electronics and Communication and a Master of Business Administration.
Vinay Manikkoth is an Applications Engineer with Cypress Semiconductor. He has a master’s degree in Microelectronics and VLSI Design from Indian Institute of Technology, Kharagpur, India.