For the past 40 years, conventional flash memory has been based on two-dimensional planar structures that make use of floating gate transistors. These structures consisted of billions of cells organised into flat rows, pushed together in an effort to minimise the size of the end device.
Within a typical 1x nanometre 128Gb 3Gb MLC device there are around 43 billion NAND cells – enough to store 16GB of data. When designing these NAND flash cells, the key objective is to shrink them down as far as possible, so that more cells can be compressed into the same space. Through this process, designers have been able to produce NAND flash memory with ever-greater capacities.
In 1999 the first storage with NAND flash was developed based on a design rule of 120nanometer. Through shrink technology, this design rule was ultimately reduced down to the 10nanometer-class, allowing manufacturers to fit 64 times more cells into the same storage space. Generally speaking, this reduction in size has followed Moore's Law, with the number of cells roughly doubling every two years.
As manufacturing process technology has proceeded to 10nm-class and beyond, engineers have grown increasingly aware that they may one day reach a potential “scaling limit”. While continuing to decrease in size, as ever more cells are crammed into the same physical space, a number of significant challenges start to arise.
Most common amongst these challenges is the growing likelihood of cell-to-cell interference. As the space between cells decreases, they begin to affect each other’s behaviours via a coupling effect. This interference can ultimately lead to potential damage and even data corruption.
Generally when the cells have a design rule of 30 nanometres or more, cell-to-cell interference can be easily controlled through the design effort. As the design rule becomes smaller however, the probability of data corruption dramatically increases.
In addition to the challenges of interference, the shrinking of NAND cells also leads to growing difficulties in the photolithography process. As the design rule gets lower, it becomes increasingly difficult to find an appropriate light source. As one example, the light source for a 40nm class design rule can be used to inscribe photo mask patterning on a NAND wafer without any issue.
Once the design approaches 1x nanometre however, this light source cannot penetrate the smaller pattern. As a result, the development of an adequate light source for 1xnanometer patterning requires huge investment in new equipment.
To read more of this external content, go to “Addressing the scaling limit.”