Overlooking design-for-test can lead to costly PCB design rework - Embedded.com

Overlooking design-for-test can lead to costly PCB design rework

In the design phase of many printed circuit boards, the engineer is more interested in functional testing, making sure that the system he has developed meets the original specifications. Little thought may be given to incorporating features that allow visibility into the board to make sure it meets specs of the in-house manufacturing associates or the outside manufacturing company.

At the design and layout stage the assumption is often made that manufacturing will be flawless, allowing the development team to concentrate on functional tuning of the product. Unfortunately the test engineer at the manufacturing house is seldom given due consideration during design.

The result is that when manufacturing personnel test the assembly of that particular board, it is a difficult, if not impossible, task. The critical access or test points that would make the board more easily testable are not there. If DFT requirements had been considered, the probes of a flying probe tester would have incorporated the necessary contact points to make contact on the circuitry for measurement purposes, as shown in Figure 1 .

Figure 1: DFT’s main objective is to provide contact points on circuitry for probes of flying probe tester.

By not giving assembly and manufacturing those critical access points, the result is low test coverage and, in worst cases, the board will go through manufacturing missing all the critical tests it needs, such as 30 percent test coverage when a typical PCB should be 70 to 80 percent accessible with testing probes. In the example shown in Figure 2 , a high-frequency, high-speed board lacks the necessary extra test points or the possibility of making the pad sizes larger.

Figure 2: High-frequency, high-speed PCB lacks extra test points or possibility of creating larger pad sizes.

About eight hundred 0201-type passive components are at the center of this DFT issue. Table 1 shows land pattern sizes for the 0201 component in this particular design. The three columns, C, X, and Y, show IPC recommended sizes for the land pattern. As shown in the Y column, the 0201 component used on this particular board is almost half the size in the Y direction. Instead of being 0.6 millimeters (mm), it is 0.325 mm. The standard 0402-type package size is about half the size of the 0201 component itself.

At the PCB design stage, the 0201 pad was made smaller for signal integrity purposes. The test point and shape of the pad affect the impedance. If the pad is were thicker or bigger, then the impedance would be less. In this design, the 0201-type pad is made smaller to avoid impedance mismatch, and as a result, there is no additional area on the pad for test probes to hit.

Figure 3a shows the smaller pad sizes used for the 0201 in this design. There is no extra land area that can be used to probe the circuitry and measure this component’s values. However, there were vias covered completely with solder mask to prevent solder from flowing into the vias.

Figure 3a: Smaller pad sizes for 0201 passive components used to avoid impedance mismatch. But no pad area is left for test probes to hit and measure 0201's values.

To open up areas for test probes, certain after-the-fact design adjustments are necessary. Rather than covering the entire via with solder mask, a strip of the solder mask is left at the end of the component pad where the solder mask would originally be located. Then the remaining portion of that via pad is left open to allow the test probe to hit the exposed copper as shown in Figure 3b .

Figure 3b: Design adjustments made to open up test probe areas for 0201 passive components. Via pad is left open for test probe to hit exposed copper.

Changing the solder mask involves several steps. Normally, the solder mask is defined at the CAD level, and the fab shop building this board normally alters the solder mask per their requirements or to meet the industry specific standards for manufacturing the board. If they are sufficiently savvy about the fabrication process, PCB designers will specify the solder mask in their layouts. However, most often, the CAM (computer-aided manufacturing) technician or engineer defines the solder mask.

In this case, the fab shop’s requirement was to have a laser direct imaging (LDI) process since the tolerance involved in this solder mask change is minimal: at about +/-1 mil. Since the solder mask change was so very small, it was imperative to use LDI, and those changes are made at the CAM level to achieve the desired results.

In this case study, the solution was achieved without changing any electrical portions of the board and only involved minimal changes. By making changes to the solder mask, a considerable number of nodes were opened and coverage increased from 30 percent to 79 percent.

Another technique
In some highly complex, high-speed PCBdesigns, finding and squeezing out minuscule areas for test probes tohit the circuitry can be challenging. One approach is to change acircular ring around a via to a square shape, as shown in Figure 4 . Thereis less area in the circular pad compared to a square pad of the samesize. But with the square pad, the test engineer can add additionalcopper areas at the corners, allowing proper probing sites.

Figure4: Finding test point areas on highly complex PCB designs ischallenging. Changing a circular ring around a via to a square shapeprovides more copper areas at the corners for prober probing sites.

Poor DFT basis for defects
Asseen in the earlier example, any small change in inductance,capacitance, or resistance – and thus a small change in impedance -triggers a major signal integrity issue. That is why it’s even moreimportant for high-speed designs to have the passive components properlyinstalled so they can be correctly tested.

In an idealscenario, all the wire routing networks (nets) on the board should havetest points that are accessible from one side of the board, preferablythe lightly populated side.

One technique is exposing traces atlocations for the probe to make contact without adding any feature tothe path of the signal. The risk involved is the danger of peeling offthe trace with multiple hits of probe or even with just a single hit ifthe width is 0.1mm or less.

Performing effective test atmanufacturing assures the functional testing personnel that there areminimal to no defects in the manufacture of a PCB. If test coverage islow or critical paths aren’t tested then an extra amount of time isconsumed debugging the board for manufacturing defects.

Anin-circuit test (ICT) or flying probe test is applied to provideassurance that all components are present at their assigned positionswith their desired value. The values of resistors and capacitors aretested, as well as the value of the inductance when required. To testthe impedance of the entire path of a signal, a nodal impedance test isperformed. Each node is tested against the ground or referenceplane. This ensures all the desired impedance levels are maintained atthe manufacturing stage.

In addition to properly testing thosevalues, the flying probe test can also detect significant defects orfailures on the PCB. Short circuits (electrical circuits that allow acurrent to travel along an unintended path) are most common, especiallyin modern PCB designs using fine pitch components, where they occurbetween two component pins. In the case of a ball grid array (BGA)package or quad flat package (QFP), the short occurs between balls orspheres.

Open circuits (electrical circuits that lack a completepath between the terminals of their power source) are the next mostcommon problem. On a PCB, open circuits occur when there is an impropersolder connection between the pad and pin of a component. The third mostcommon failure is installation of the wrong component, due to either aprogramming error in the pick-and-place machine or a human error, suchas when a wrong component if inadvertently used, In addition, componentsmay have the wrong orientation because they were placed at the wrongrotation on the reel holding them (Figure 5 ).

Figure5: Flying probe and ICT tests can catch wrong componentorientation. Components are placed at wrong rotation on reel holdingthem.

Design considerations for best DFT
Withoutquestion, the primary consideration is to provide the test engineer allthe necessary access points so he or she can properly write the testassociated with a particular design. Probe points are the key areas thatneed to be considered in a design. Special attention has to be given tothose areas where it’s not possible to have test points for every net.However every effort should be made to assure that critical traces havethe necessary probe access points.

It’s also important for thePCB designer to take advantage of all the advanced DFT features builtinto high-end CAD tools that allow designers to define test points andreport whether or not nodes are accessible. The designer can then lookat each node individually to decide whether or not it is important toallow access.

It’s important to note that placing a test pointon a high-speed signal path can deteriorate its signal integrity andresult in an impedance mismatch. In cases like this, the designer isprone to lean more toward maintaining the signal integrity necessary toproduce a functional design, rather than worrying about testingrequirements for that design when it goes to manufacturing.

Inaddition to the ones described here, there can be a number of differenttradeoffs such as the amount of board level cross talk to allow versusthe cost of manufacturing. But to make the right decisions, it isimportant to have an effective DFT strategy in place based on a closepartnership and working relationship between PCB design and testengineering.

Faisal Ahmed is a PCB layout engineer atNexLogic Technologies, Inc., San Jose, CA. He received his BSEE fromN.E.D. University of Engineering and Technology in Karachi Pakistan. 

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