Packaging: Embedded design challenges ahead -

Packaging: Embedded design challenges ahead


The most under-appreciated members of any embedded systems design team may be the packaging specialists. Until I read two recent contributions to “Xilinx’s Virtex-7 200T FPGAs” by Jack Ganssle, and “3D-IC Design ” by Samta Bansal, I was not completely aware of the daunting challenges packaging designers face and how much coordinated effort is required between all team members.

In his column , Jack was impressed with the sheer size and capability of the Xilinx FPGA and how the designers had used through-via 3D-IC techniques . However, I was more impressed with what this required in terms of packaging and pin-out: a grid array of 1,925 solder balls, of which 1,200 are for I/O, and 56 decoupling capacitors to filter and protect the signals going in and out.

What really blew my mind, though, was Bansal’s description of the many chip and package level options being considered to combine with 3-D ICs to further increase functional density: stacks of die with wirebonds, System- In-Package, Package-in-Package, and Package-on-Package using micro-bumps, flip-chip bumps and package bumps, to name a few.

My Editor’s Top Picks for recent articles that best describe the packaging challenges ahead are:

Taking on the 0.3 mm ultra-fine pitch device challenge
Reduce SoC device/package leakage/power
Using chip-on-chip SiP techniques in embedded designs

To keep up to date on packaging technologies, be sure to register to attend “DesignCon 2012: where chipheads connect” to be held ten weeks from now in Santa Clara, Ca.

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