Parallelizing sequential C code and partitioning it across multiple processors - Embedded.com

Parallelizing sequential C code and partitioning it across multiple processors

Are you going to DAC 2016, which takes place June 5-9 in Austin, Texas? Are you interested in automatically parallelizing your sequential C code and then automatically partitioning it across multiple heterogeneous cores? In this case, you might want to arrange to meet and chat with Maximilian (Max) Odendahl, the CEO of Silexica Software Solutions (you can email Max at ).

But perhaps I'm getting ahead of myself. A couple of weeks ago, while having my mind boggled at the Embedded Vision Summit (see Day 1 and Day 2), I ran into all sorts of interesting people. One with whom I immediately bonded was Maximilian Odendahl.

After spending a happy few minutes discussing how the name Max is used for pretty much every dog and every robot in every science fiction film, we turned our attention to all of the amazing embedded vision applications and technologies on display in the expo area of the summit.

We next moved on to consider the compute-intensive requirements of applications like baseband processing, autonomous driving (ADAS), and embedded vision and augmented reality. It turns out that the guys and gals at Silexica have some very interesting technology in this area.

As an aside, although the initial Silexica team started with PhDs from RWTH Aachen Germany, they now boast compiler, C++, and Eclipse experts from all over the world (e.g., Colombia, Ireland, Costa Rica, India, and Greece).


Some members of the Silexica team (Source: Silexica)

First, they have tools like SLX Parallelizer, which performs C code partitioning by analyzing control and data flow within the original sequential code, exposing a maximum amount of parallelism. An additional automatic performance estimation allows a fast and accurate prediction of application hotspots and that performance gains associated with the identified parallelism.


Sequential code partitioning (Source: Silexica)

Next, they have tools like SLX Explorer, which facilitates multi-core selection and design space exploration. Of course, platform exploration and selection is very dependent on the target application. In the case of embedded vision, for example, your choices include (but are not limited to) processors like the Movidius myriad2, CEVA-XM4, Videantis multicore vision IP, Synopsys EV Processors, Tensilica Vision DSP, TI TDA2x/3x with EVE (Embedded Vision Engine), Renesas H2/H3 SoC, and… the list goes on.


Multi-core selection and design space exploration (Source: Silexica)

One very important point to note is that Silexica's tools are not intended to replace your existing tools and flows; instead, they “sit on top” of these tools and flows.

The reason I'm waffling on about all of this here is that Max will be giving a presentation on Automated SW Distribution for Automated Driving as part of the Design Automation on the Road Towards Automated Driving track.

Although Silexica won't have a booth at DAC, Max says that if anyone is interested in talking about automatically parallelizing sequential C code and automatically partitioning it across multiple heterogeneous cores, then they can email him at to set up a meeting. If you do get to meet Max, tell him that Max says “Hi” (LOL).

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