PCB Design Tool - effective post-layout simulation - Embedded.com

PCB Design Tool – effective post-layout simulation

PCB designers faced with increasing clock speeds, faster switching devices and increasingly dense layouts need effective post-layout simulation and verification if unnecessary design iterations are to be avoided; design 'rules-of-thumb' are no longer accurate enough. CADSTAR SI Verify , a new tool within Zuken 's CADSTAR PCB design suite, provides these capabilities at up to Gigabit speeds.

The tool uses a transmission line simulation approach to analyze reflection and crosstalk effects and also facilitates real interconnect timing and delay analysis. It incorporates a graphical scenario editor, layer stack definition for optimization of impedances and layers, an EMC device library, and the option to perform interactive simulation or batch simulation.

CADSTAR SI Verify enables Fast Fourier Transform (FFT) analysis in time or frequency domains and provides sophisticated crosstalk analysis and optimization of track spacing. It also provides for simulation of differential pairs or positive-referenced emitter-coupled logic (PECL) and a parameter sweep helps determine the ideal values of passive components or transmission line lengths to achieve the desired electrical performance of nets. The tool is fully integrated into the CADSTAR design flow and engineers need not be signal integrity experts to be able use it.

Zuken Ltd , Bristol, Glos BS34 4RF, UK.

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