Phaselocked loop design through the decades – Part 1
PLLs (phaselocked loops) are among the most commontypes of analog/mixedsignal circuits on today’sSOC (systemonchip) ICs. PLLs are essential companionsto the digitallogic circuits and processorson these chips.
Today’s SOCs are likely to integratemany types of PLLs. Like the digital circuits on theseSOCs, the continual advances in process technologybenefit analog/mixedsignal circuits. Clever designers havemade many contributions that have increased the performance ofanalog/mixedsignal circuits, and PLLs in particular, beyond whatyou would expect from simple scaling.
The advances in process technologyand circuit techniques have allowedPLLs to become smaller and consumefar less power per megahertz of outputfrequency and to achieve better performancethan that of PLLs of decadespast. The advances have made possibleapplications for PLLs, includingSERDES (serializer/deserializer) circuitsand RF integration.
A bit of history
PLLs date back to the 1920s, but theirpopularity and applications took off withthe introduction of the monolithic PLL.The 4046 CMOS Micropower PLL,which RCA introducedin the 1970s, is one of the early PLLICs. These ICs found use in many applications,including frequency synthesis,FM demodulation and modulation,voltagetofrequency conversion, anddata synchronization. The 4046 integratedtwo types of phase detectors—a linear mixer and an edgetriggeredphase/frequency detector—with a VCO(voltagecontrolled oscillator) and anoutput buffer that allowed designers touse the tuning voltage for demodulation applications.
By adding an externaldivider, you could configure the circuitas a frequency synthesizer, with a rangefrom tens of kilohertz to slightly morethan 1 MHz and a power dissipation oftens of microwatts to 1 mW. Designershad to add an external loop filter, butthat requirement provided flexibility insetting the loop dynamics.
Fastforward to today. The mostcommon type of PLL for SOC applicationsis the frequencymultiplying PLL.This type of PLL generates a highfrequencyclock from a lowfrequency crystalor another reference. Applicationsfor frequencymultiplying PLLs arewidespread and include logic clockingand RF localoscillator synthesis. It iscommon for a modern SOC to containfive to 10 of these PLLs.
It is interesting to compare a modernSOC multiplying PLL with one using the4046 chip, an external feedback divider,and the external loopfilter components(Figure 1 ). The 4046based circuit wouldconsume several hundred square millimetersof PCB (printedcircuitboard)area, whereas this SOC PLL has an area ofapproximately 0.07 mm^{2} —roughly 2000times smaller. These fully integrated PLLsalso include more features. The typicaloutput frequency is 2 GHz, or about 2000times larger, and the power dissipation issimilar. The modern circuit also offerspower consumption that is approximately2000times better in terms of watts permegahertz.
Most of the advances in frequency,power per megahertz, and area are duesimply to advances in process technologyand would not be surprisingto anyone familiar with Moore’s Law.The SOC PLL in Figure 1 integratesmore than 25,000 transistors, whereasthe 4046 chip used roughly 5.6 mm^{2} for its 150 components (Reference 1).The ability to integrate many moretransistors has enabled analog/mixedsignalcircuit designers to exercise theircreativity and increase their designs’performance.
Advances in resolution
Most frequencysynthesis PLLs incorporatea predivider (÷N) and postdividers(÷P), plus a feedback divider (÷M),generating a frequency of F_{IN} ×M/(N×P).The resolution in output frequency isF_{IN} /(N×P). Making these dividers largeryields finer resolution. However, thisimprovement comes at a cost in otherimportant performance parameters.
As N increases, the PLL comparisonfrequency decreases, and PLL bandwidth must decrease proportionally. A decreasein bandwidth increases the lock timeand PLL area—because the loop filtermust grow—and the longterm jitter getsworse. Increasing P requires the VCO torun P times faster. A P value of two tofour is common for many applications.For large P values, however, the requiredVCO frequency could exceed the processlimitations.
Additionally, the power inthe VCO and dividers scales with theVCO frequency. So, using the postdividerto achieve fine frequency resolution hasserious drawbacks, as well. One way toavoid these tradeoffs is to use a nonintegerdivide value for one of the dividers;fractionalN PLLs employ this approach.
You can achieve a fractional dividervalue of, for example, 10.25 by the followingset of divider values: 10, 10, 10,11, 10, 10, 10, 11, and so on. You canimplement such a variableratio dividerwith a simple accumulator (Figure 2 andReference 2). Next, you must decidewhich of the three dividers should befractional. The first choice—the postdivider—has the problem of transferringthe noise or jitter of the divider modulationdirectly to the output—usually,an unacceptable situation. Assumingthat the PLL holds the VCO frequencysteady, the output period would vary bya whole VCO period. To minimize jitter,the VCO would need a small period, correspondingto a high frequency.
The predivider and postdivider arebetter choices for modulation because,in these configurations, the PLL actsas a lowpass filter on the noise or jitter associated with modulating the feedbackdivider. The following equationrelates the VCO frequency and the referencefrequency: F_{VCO} =F_{REF} ×M/N. Formost practical PLLs, the value of M islarger than that of N, meaning that theVCO period is smaller than the referenceperiod. So, dithering the feedbackdivider has a smaller effect than ditheringthe reference divider by the ratio ofM/N, making this choice the most commonone. Circuits of this type, usingmultiple ICs, began to appear in the late1970s and early 1980s.
In the example of the sequence forgenerating a divider value of 10.25, thedivide pattern repeats every four cycles.This approach generates a noise toneat F_{REF} /4. If you use the same methodto generate an effective value of 10.01,then a tone would appear at F_{REF} /100.The spectral tone is problematic formany systems that would like to takeadvantage of the fine frequency resolutionthat fractionalN PLLs provide.If this noise tone falls to a frequencybelow the PLL’s bandwidth, considerablelongterm jitter, unacceptable inmany applications, can result.
A breakthrough in the evolution ofthe fractionalN PLL was the applicationin 1993 of deltasigma modulationto the dithering of the feedbackdivider (Figure 2 and Reference 3).The deltasigmamodulation noiseshapingtechnique can push dithering noise to high frequencies, at whichthe PLL can easily filter it. Using thistechnique, designers have created PLLswith nearly undetectable fractional spurtones. Integrated fractionalN PLLs stillfall short of the performance of similarintegerN PLLs, however, because of thelow bandwidth necessary to filter thedithering noise. With lower bandwidth,the PLL is less able to suppress the phasenoise of the VCO.
The dithering noise from the deltasigma modulator is a pseudorandompattern. A recent refinement inintegrated PLLs cancels this noise byapplying a correction directly to theloop filter. Industry literature reportsimprovements of 10 to 20 dB, allowingdesigners to increase the bandwidth offractionalN PLLs, with benefits in circuitarea, phase noise, and jitter. In thisway, the performance of fractionalNPLLs can approach that of integerNPLLs. The SOC PLL in Figure 1 takesadvantage of Moore’s Law to integrate a24bit modulator, allowing the outputfrequencyincrement to be 0.06 ppm orsmaller—an extremely fine resolution.
Advances in PLL quality
The LCoscillator circuit predates ICtechnology. However, the integrationof LC oscillators had been problematicuntil only the last 10 to 15 years.The first problem had to do with theinductor itself. In process nodes largerthan 0.25 microns, it was uncommonto have more than three metal layers,and the typical interconnect metal wasaluminum.
Inductors in this process had relatively high series resistance,resulting in a low Q factor. The limitednumber of metal layers also meant thatthe inductor was physically close to thesilicon surface. This situation in turnmeant that these inductors had significantparasitic capacitance and hence alow selfresonant frequency.
To read Part 2 in this series, go to “Current, future work.“
References 

Jeff Galloway is a principal and cofounder of Silicon Creations, LLC . He received is technical education Georgia Institute of Technology (BSEE) and Stanford University (MSEE) and previously worked as design enginner on a variety PLL, CDR, SERDES, ADC designs in CMOS, BiCMOS and bipolar technolgies.
Andrew Cole is VP Engineering at Silicon Creations and has previous IC design experience at Foveon, Virtual Silicon, and Philips Semiconductor and has extensive experience in the design of amage sensors, displays, analog, mixed signal IC and SOC development.
This article has also been published on the EDN Network.