# Phase-locked loops in an IC-based clock distribution system: Part 2 – Phase noise

In **Part 1** of this series, we discussed phase-locked loop applications and advantages in clock distribution systems compared to conventional oscillators. In this article and the next we will discuss significant parameters of PLL-based clock distribution systems that need to be considered during design (such as the importance of accurate timing of the clock when exercised).

Wide deviations in clock positions may cause a system to malfunction. These deviations in time domain are referred as “jitter”. Jitter can be classified into categories such as period jitter, cycle-cycle jitter, RMS jitter, long-term jitter, and phase jitter. Here we will keep the focus on phase jitter, which when examined in the frequency domain is also referred to as “phase noise”.

**Defining phase noise and phase jitter**

Phase noise and phase jitter are the key parameters for any clock distribution system, as the quality of the clock signal is heavily dependent upon its phase noise and jitter. The maximum speed of digital I/O is limited by timing errors in clocks. With continuing advances in technology and increased timing precision requirements, it is essential to have clocks with accurate edges and high stability.

Ideally, there should no variation in clock edges from their expected position. In practice, clock sources are highly affected by noise, which in turn causes variation in clock edges from their ideal position. This is called “jitter”. PLL-based frequency synthesizers are mainly designed to ensure the accuracy of the output frequency under specified operating conditions. One of its critical requirements includes phase noise and phase jitter performance, where phase noise represents clock signal noise in the frequency domain and jitter is the time domain representation of clock signal instability. “Time” and “phase” can be used interchangeably to quantify jitter and phase noise.

Excessive jitter in a system causes higher bit error rates that may exceed system-level requirements. RF and A/D data conversion applications require very low phase noise clocks. In RF applications, increased phase noise can create channel-to-channel interference, degrading RF signal quality. In ADC applications, higher phase noise can limit the signal-to-noise ratio (SNR) and increase quantization error.

One of the major issues being faced by PLL designers is the phase noise phenomenon. Phase noise is an undesirable entity that is present in all real-world oscillators and signal generators that can cause distortion or complete loss of incoming information in traditional receivers. It is therefore necessary to understand and to quantify phase noise so that its effects on the higher level product are minimized.

**Understanding phase noise **

To understand what phase noise is, let’s start by looking at an ideal sinusoid signal. A sinusoidal wave is the fundamental form of a periodic analog signal. A sinusoid signal can be expressed as:

where A= Peak amplitude of signal, f= Frequency and Φ = initial phase (i.e., the absolute position of the waveform relative to an arbitrary origin). Phase is measured in degrees (º) or radians. A time domain plot of any real-world signal specifies the signal amplitude at any instant of time, and it does not express explicitly information of the signal’s phase or frequency.

On the other hand, by taking the Fourier transform of a signal, we can obtain signal information in the frequency domain, which represents the signal’s peak amplitude with respect to the frequency components that comprise it. The time domain and frequency domain are just two ways of representing a signal to capture different information. When talking about time variation in a signal, one can be considered to be talking about phase or frequency variation, which can be correlated as:

Where is deviation in phase, is deviation in period, and T is the overall period of the signal under observation.

As shown in **Figure1(a)** , an ideal sinusoid signal is a monotonic wave. This means it will have only one frequency component with its entire power confined to it. This can be seen by taking its Fourier transform. However, the signal will have some degree of fluctuation in amplitude as well as in phase caused by environmental and/or signal source noise.

By Fourier expansion, we can see that any signal can be broken into sinusoid signals of different frequency and amplitude. Hence, the Fourier transform will show the power spectrum distributed across multiple frequencies. **Figure1(b)** demonstrates the sinusoid signal, both in time and frequency. Where the signal power is distributed across a frequency band, this means the signal carries multiple undesired frequency components.

(b)

*Figure 1: (a) Ideal signal (b) Real signal in time and frequency domain*The phase noise of an oscillator is short-term instability and is best described in the frequency domain where the spectral density is characterized by measuring the noise sidebands on either side of center frequency. In practice, most phase noise measurements show a single sideband. As discussed above, an ideal signal shows a single pulse at exactly its carrier frequency with all of the signal power contained within that pulse. With a real-world signal, the noise causes the power to spread out across a wider frequency band.

Phase noise is typically expressed in dBc/Hz and is calculated as the ratio of noise power at a given offset frequency from the carrier in 1Hz bandwidth to the carrier power. The term “dBc” stands for decibels below the carrier and is used in defining the sideband phase noise properties.

** ****Figure 2** shows a typical output frequency spectrum of a non-idealoscillator. The spectrum shows the noise power in a 1-Hz bandwidth atoffset frequency COURIER f0 and carrier power at fc.

*Figure 2: Oscillator power spectrum due to phase noise*Thisfigure shows the double sideband definition to introduce the concept,but in practice most phase noise measurements are done on a singlesideband. It is expressed by the formula:

Thesephase variations can be discrete (deterministic) or continuous(random). Discrete variations are called spurious frequencies (spurs)and, as shown in the spectral density plot in** Figure 3** , are mostly related to known phenomena in the signal source such as power line frequency, vibration frequencies, etc.

Sincethese are based on known process, they are called deterministic and canbe avoided by taking proper care during system design. On the otherhand, continuous phase fluctuations are caused by random noise phenomenasuch as environmental noise, which includes white noise and flickernoise.

**Figure 3: Phase noise plot with spur****RMS phase jitter **

Phasenoise and phase jitter are closely linked. Phase noise is the frequencydomain representation of clock noise. Phase jitter, on the other hand,is the time domain instability of the clock signal. RMS phase jitter isobtained by integrating the phase noise over the offset frequency rangeof interest from the phase noise plot.

In a square wave, most ofthe energies are located at the carrier frequency. However, some signalenergies leak out over a range of frequencies. Phase jitter is theamount of phase noise energy contained between two offset frequenciesrelative to the carrier (fc). **Figure 4** shows a phase noise plot(note that it shows single side band only) and integration range (fromf1 to f2) that is used to determine the RMS phase jitter. The offsetfrequency range depends on application requirements.

**Figure 4: Integration of phase noise to obtain phase jitter**Thefirst step in calculating the equivalent RMS jitter is to obtain theintegrated phase noise power over the frequency range of interest (i.e.,the area under the curve). The curve is broken into a number ofindividual areas, each defined by two data points. Generally, the upperfrequency range for the integration should be twice that of the samplingfrequency in the desired application, say an ADC (assuming there is nofiltering between the oscillator and the ADC input). This approximatesthe bandwidth of the ADC sampling clock input.

Selecting thelower frequency for the integration also requires some judgment. Intheory, it should be as low as possible to get the true RMS jitter. Inpractice, however, the oscillator specifications generally will not begiven for offset frequencies less than 10 Hz or so, though this willcertainly give accurate enough results. A lower frequency of integrationof 100 Hz is reasonable in most cases, if that specification isavailable. Otherwise, use either the 1-kHz or 10-kHz data point.

Insystem designs requiring low jitter sampling clocks, the cost of lownoise dedicated crystal oscillators is generally prohibitive. Analternative solution is to use a phase locked loop (PLL) in conjunctionwith a voltage-controlled oscillator to clean up a noisy system clock.

Anarrow bandwidth loop filter in conjunction with a voltage-controlledcrystal oscillator (VCXO) typically gives the lowest phase noise. ThePLL tends to reduce the “close-in” phase noise while at the same timereducing the overall phase noise floor. Further reduction in the whitenoise floor can be obtained by following the PLL output with anappropriate bandpass filter. Taking the integrated area with the phasenoise over the desired offset frequency range (f1 to f2), the RMS phasejitter can be calculated using the following equation:

RMS Phase jitter (radians) =

RMS Jitter (sec) =

**Additive phase jitter **

Now,instead of a clock generator, let’s assume a clock buffer is used todistribute multiple copies of a clock from a single source clock input.For high performance clock devices, performance is not measured by theamount of phase jitter present at the output because this value isdependent on the input phase jitter of the source. Instead, the additivephase jitter is used to evaluate the quality of these sources.

*Additive phase jitter* accounts for the amount of phase jitter that is contributed by thebuffer device to the total output phase jitter. In this way, the bufferdevices can be compared without accounting for the quality of input usedwhen taking the measurement.

The *clock phase jitter* is acritical parameter in many system designs, so it is important that wecan accurately measure the phase jitter contributions of each component.Depending on the hardware and test set available, one of the simplestmethods for calculating the additive jitter of a clock tree component isthe “sum of squares” method.

By measuring the total RMS phasejitter at the output of the device under test (DUT) and then measuringthe RMS phase jitter of the source input signal to the DUT, we cancalculate the additive RMS jitter of the DUT by the following equation:

whereΦ indicates the RMS phase jitter. It is best to have an extremelyhigh-quality low-phase noise reference when using this method so thatthe vast majority of the total jitter is contributed by the DUT ratherthan the source input. To obtain the level of performance needed, anOCXO is used as the reference source.

**Part 1: Phase-locked loops in an IC-based clock distribution in system – The What and Why**

**Sanjay Agarwal** is Senior Product Engineer in Timing Solutions, **Cypress Semiconductor, Bangalore** .He holds a Master of Technology degree from Indian Institute ofTechnology Kanpur specialized in Electronic Materials, devicefabrication and characterization. He has authored numerous technicalarticles in semiconductor electronics publications. He can be reached at.

**Ashish Kumar ** ispresently working with Cypress Semiconductor India Pvt. Ltd. as a StaffProduct Engineer. He holds Bachelor degree in 'Electronics &Communications Eng'. He also completed PG Diploma specialized in'Advanced VLSI Design'. His interests are in making hobby electronicprojects, debugging circuit boards, and dealing with complex analog anddigital circuits. He can be contacted at: **ashi@cypress.com.**