In Part 1 and Part 2 we dealt with the role of phase-locked loops in IC-based clock distribution systems and how phase noise and jitter affect their performance. In this article we will look at the many other noise sources due to thermal, shot, flicker, white, reference, voltage controlled oscillator, phase detector, frequency divider, and charge pump effects and how to deal with them.
The many sources of phase noise
Generally oscillators are characterized in terms of their single-sideband phase noise as shown in Figure 1 . Phase noise (dBc/Hz) is plotted as a function of offset frequency f0 on a logarithmic scale.
The actual curve is approximated by a number of regions, each having a slope of 1/fx, where x = 0 corresponds to the “white” phase noise region i.e. slope of the curve is 0 dB/decade. For x = 1, phase noise region is called “flicker” and its slope is –20 dB/decade. Similarly, other regions correspond to higher values of x. A region with a higher value of x is closer to the carrier frequency.
Figure 2 shows a plot of phase noise for a PLL-based clock generator. It should be noted here that this plot can be approximated to different noise regions as shown in Figure 1 above.
The output signal of an oscillator, no matter how good it is, will contain all kinds of unwanted noise signals. Some of these unwanted signals are spurious output frequencies and harmonics. The noise can be random or deterministic in both the amplitude and phase of the signal. Here we will look into the major sources of some of these unwanted noise signals.
Oscillator noise performance is characterized as jitter in the time domain and as phase noise in the frequency domain. Which one is preferred, time or frequency domain, may depend on the application. In radio frequency (RF) communications, phase noise is preferred while in digital systems, jitter is favored. Hence, an RF engineer would prefer to address phase noise while a digital engineer wants jitter specified.
Again note that phase noise and jitter are two linked quantities associated with a noisy oscillator and, in general, as the phase noise increases in the oscillator, so does the jitter. The best way to illustrate this is to examine an ideal signal and corrupt it until the signal starts resembling the real output of an oscillator. The rest of the article analyzes major souces of noise.
When two objects are kept at different temperatures, there will be exchange of energy until they achieve thermal equilibrium. Thermal noise (kTB) is caused by Brownian motion of electrons due to thermal excitations or other charge carriers in passive and active components of the system such as resistor, capacitor, sensors, and electrochemical cells. Thermal noise is directly proportional to temperature and bandwidth so with increase in temperature and bandwidth, thermal noise increases. The magnitude of thermal noise is given by
where = root mean square noise, = frequency bandwidth (Hz), k = Boltzmann constant (1.38 x 10-23 J/K), T = temperature in Kelvin, R = resistance in ohms of the resistive element.
Thermal noise can be decreased by narrowing the bandwidth, by lowering the electrical resistance, and by lowering the temperature of instrument components. Thermal noise is virtually flat with frequency.
In a forward-biased PN junction, charge carriers require a certain amount of energy to cross the energy barrier. Shot noise is represented by discontinuous current flow across PN junction potential barriers. It is encountered wherever charge carriers cross PN junction.
where, irms = root-mean-square current fluctuation,
I = Average direct current
e = Charge of electron i.e.1.60 x 10-19 C
= band width of frequencies.
Shot noise can be reduced by reducing the bandwidth.
All electronic components, especially amplifiers and logic devices, generate a combination of shot noise and thermal noise. It is commonly found in diodes and transistors. As discussed above, shot noise is caused by random hopping of charges across a potential barrier within a PN junction. On the other hand, thermal noise is unaffected by current flow. It is caused by the random thermal motion of carriers, within a MOSFET's gate and channel resistance. The thermal noise power is directly proportional to the resistance and temperature. The effect of shot noise and thermal noise on timing jitter becomes significant as the operating bandwidth of modern components is in GHz range.
Noise flicker is represented as 1/f andintercepts the thermal noise floor at the offset corner frequency fc. Itis spectrally related to 1/f and found in all active devices, as wellas some passive components such as carbon resistors. Flicker noise ischaracterized as having a magnitude that is inversely proportional tothe frequency of the signal being observed. The cause of flicker noiseis not well understood and is recognizable by its frequency dependence.Flicker noise becomes significant at frequency lower than about 100 Hz.Flicker noise can be reduced significantly by using wire-wound ormetallic film resistors rather than the more common carbon compositiontype.
The power spectrum of noise exhibitsconcentration of noise power at any given frequency. Many noise sourcesare “white” i.e. the spectrum is flat, even for very high frequencies.In other words, white noise is constant and independent of frequency.The signal power for a constant bandwidth does not change with change infrequency. When plotted versus frequency, white noise is a horizontalline of constant value as shown in Figure 1.
Phase noise in PLL
APLL is a type of oscillator and, as in any oscillator design, frequencystability is of utmost importance. For a high performance clockdistribution system, phase noise is of key concern since it directlyaffects the entire performance of the system. The noise sources canrepresent either the noise created by individual blocks due to intrinsicnoise sources, or the noise coupled into the blocks from externalsources, such as noise from power supplies and substrate noise. Inreality, all the blocks in the PLL contribute, more or less, to theoutput phase noise.
Let’s recall the PLL block diagram (Figure 3 ) again before studying the blocks that contribute to the overall phase noise.
Reference and VCO noise
PLLnoise is dominated by two sources, namely the reference oscillator andVCO (Voltage Controlled Oscillator) which contribute to the overallphase noise of the PLL. Noise sources of reference include thosegenerated by timing sources, PCB noise coupling, and power supply noise.VCO noise sources include loop filter components, VCO amplifier noise,and power supply noise.
An ideal VCO would have no phase noise,and it will show a single spectral line when viewed in the frequencydomain. However, this is not the case in practice as the jitter on theoutput of VCO would cause the spectrum to spread out and introduce phasenoise. VCO noise can be best understood by Leeson’s equation .By studying it we can uncover the areas to reduce VCO noise. Leeson’sequation describing an oscillator’s phase noise spectrum is given as:
is the ratio of power at offset
fm in 1Hz band to the total output power generated by oscillator in dBc/Hz
fo is carrier frequency
fm is offset frequency
fc is the Flicker corner frequency
Q1 is the loaded Q of resonator (loaded Q means quality factor including effects of external components)
F is the noise factor
kT is the Boltzman constant at room temperature
Ps is the average power at input of oscillator
R is the equivalent noise resistance of tuning diode
and Ko is the oscillator’s voltage gain.
By observing Leeson’s equation, we can identify points of phase noise optimization for an VCO:
- The loaded Q of the tuned circuit should be maximized. A large inductor in series resonant circuit or a large capacitor in parallel resonant circuit design can be considered to achieve this. A 10dB increase in loaded Q will result in 20dB improvement in phase noise.
- A varactor diode of low equivalent noise resistance must be chosen. Also, a varactor with less non-linearity is recommended.
- The VCO tuning gain should be kept at the minimum value required.
- An active device with low noise figures at low frequency and with low flicker corner frequency must be chosen.
- A high input power for oscillator will help reduce noise.
Whena PLL is used as a clock synthesizer, it helps attenuate the noisefrom the input source and generates a low noise output. If the inputsource to the PLL has significant amount of noise, it is typicallyrecommended to filter this using a low bandwidth PLL. However, reducingthe PLL bandwidth leads to an increase in the relative contribution ofVCO noise. Generally a high quality reference source should be used in aPLL synthesizer which has better noise performance than that of theoscillator and so PLL bandwidth can be optimized.
Phase detector and charge pump noise
Phasedetectors and charge pumps in PLLs are sources of phase noise close tothe carrier frequency. In contrast, a VCO’s main contribution is in thefar region from the carrier, mainly beyond the loop filter’s cut offfrequency. Recall that a PLL in a closed loop responds as a low passfilter. Any noise in the phase detector, charge pump, or even in thereference source beyond the loop filter’s cut off frequency is generallyfiltered.
Since integrated function of Phase detector andcharge pump is to detect the phase difference between reference andfeedback from VCO output, and then produce error signal; so randomvariation in the phase of input signal makes the phase detector producethe wrong output, which is transferred through the filter and tunes theVCO wrongly, appearing as noise on the PLL output. Keeping noise fromthe reference as low as possible and maximizing the gain of charge pumpwill hence reduce the phase noise.
Frequency divider noise
Ina PLL, frequency divider noise directly appears at the input of thephase detector and experiences the same transfer function as the noiseon the input terminal. Thus this noise also contributes to overall phasenoise in the near carrier region below the cut off frequency of theloop filter. The excess noise of a digital divider can be modeled asadditive noise source at its output.
Power supply noise
Powersupply noise must be minimized to reduce phase noise in the PLL. Powersupply noise can arise from a variety of sources such as improperlydesigned regulators, PCB noise coupling, or noise within the supplysource which has not been properly filtered. This noise adds to theoverall noise of the PLL blocks.
Phase noiseis as a critical parameter that can affect the implementation of PLLsin an ICs clock distribution system. It can be minimized with carefuldesign, not only in the PLL but at the system design level as well byusing some good filtering circuits and low noise sources, and minimizingother possible noise sources present in system.
Sanjay Agarwal is Senior Product Engineer in Timing Solutions, Cypress Semiconductor ,Bangalore. He holds a Master of Technology degree from Indian Instituteof Technology Kanpur specialized in Electronic Materials, devicefabrication and characterization. He has authored numerous technicalarticles in semiconductor electronics publications. He can be reached at.
Ashish Kumar ispresently working with Cypress Semiconductor India Pvt. Ltd. as a StaffProduct Engineer. He holds Bachelor degree in 'Electronics &Communications Eng'. He also completed PG Diploma specialized in'Advanced VLSI Design'. His interests are in making hobby electronicprojects, debugging circuit boards, and dealing with complex analog anddigital circuits. He can be contacted at: .